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linux/arch/riscv
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Eric Biggers fb5b47ad53 lib/crypto: riscv: Depend on RISCV_EFFICIENT_VECTOR_UNALIGNED_ACCESS 
commit 1cd5bb6e9e upstream.

Replace the RISCV_ISA_V dependency of the RISC-V crypto code with
RISCV_EFFICIENT_VECTOR_UNALIGNED_ACCESS, which implies RISCV_ISA_V as
well as vector unaligned accesses being efficient.

This is necessary because this code assumes that vector unaligned
accesses are supported and are efficient.  (It does so to avoid having
to use lots of extra vsetvli instructions to switch the element width
back and forth between 8 and either 32 or 64.)

This was omitted from the code originally just because the RISC-V kernel
support for detecting this feature didn't exist yet.  Support has now
been added, but it's fragmented into per-CPU runtime detection, a
command-line parameter, and a kconfig option.  The kconfig option is the
only reasonable way to do it, though, so let's just rely on that.

Fixes: eb24af5d7a ("crypto: riscv - add vector crypto accelerated AES-{ECB,CBC,CTR,XTS}")
Fixes: bb54668837 ("crypto: riscv - add vector crypto accelerated ChaCha20")
Fixes: 600a3853df ("crypto: riscv - add vector crypto accelerated GHASH")
Fixes: 8c8e40470f ("crypto: riscv - add vector crypto accelerated SHA-{256,224}")
Fixes: b3415925a0 ("crypto: riscv - add vector crypto accelerated SHA-{512,384}")
Fixes: 563a5255af ("crypto: riscv - add vector crypto accelerated SM3")
Fixes: b8d06352bb ("crypto: riscv - add vector crypto accelerated SM4")
Cc: stable@vger.kernel.org
Reported-by: Vivian Wang <wangruikang@iscas.ac.cn>
Closes: https://lore.kernel.org/r/b3cfcdac-0337-4db0-a611-258f2868855f@iscas.ac.cn/
Reviewed-by: Jerry Shih <jerry.shih@sifive.com>
Link: https://lore.kernel.org/r/20251206213750.81474-1-ebiggers@kernel.org
Signed-off-by: Eric Biggers <ebiggers@kernel.org>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
History 2026-01-02 12:57:29 +01:00
..
boot riscv: dts: allwinner: d1: fix vlenb property 2025-11-22 09:19:42 +08:00
configs RISC-V updates for the v6.18 merge window (part two) 2025-10-04 10:36:22 -07:00
crypto lib/crypto: riscv: Depend on RISCV_EFFICIENT_VECTOR_UNALIGNED_ACCESS 2026-01-02 12:57:29 +01:00
errata riscv: errata: Fix the PAUSE Opcode for MIPS P8700 2025-09-19 10:33:56 -06:00
include riscv: Update MIPS vendor id to 0x127 2025-11-15 15:27:02 -07:00
kernel riscv: sbi: Prefer SRST shutdown over legacy 2025-11-16 10:37:27 -07:00
kvm RISC-V: KVM: Fix guest page fault within HLV* instructions 2025-12-18 14:03:12 +01:00
lib Crypto library updates for 6.17 2025-07-28 17:58:52 -07:00
mm riscv: ptdump: use seq_puts() in pt_dump_seq_puts() macro 2025-10-27 11:40:43 -06:00
net bpf-next-6.18 2025-09-30 17:58:11 -07:00
purgatory kcfi: Rename CONFIG_CFI_CLANG to CONFIG_CFI 2025-09-24 14:29:14 -07:00
tools riscv: Stop considering R_RISCV_NONE as bad relocations 2025-07-16 08:13:55 -07:00
Kbuild riscv: migrate to the generic rule for built-in DTB 2025-03-18 13:30:13 +00:00
Kconfig riscv: Fix CONFIG_AS_HAS_INSN for new .insn usage 2025-11-07 17:39:07 -07:00
Kconfig.debug riscv: Add tests for riscv module loading 2023-11-07 14:59:32 -08:00
Kconfig.errata riscv: errata: Fix the PAUSE Opcode for MIPS P8700 2025-09-19 10:33:56 -06:00
Kconfig.socs riscv: Add Kconfig option for ESWIN platforms 2025-09-25 08:29:05 +02:00
Kconfig.vendor riscv: Add xmipsexectl as a vendor extension 2025-09-18 20:36:00 -06:00
Makefile riscv: Remove redundant judgment for the default build target 2025-11-07 17:39:07 -07:00
Makefile.postlink kbuild: Create intermediate vmlinux build with relocations preserved 2025-03-17 00:29:50 +09:00