linux/arch/riscv/lib
Michael Neuling 5d588c6848 riscv: lib: Fix ZBB strnlen reading past count boundary
The ZBB-optimized strnlen loop loads one word ahead before checking the
aligned boundary:

    REG_L   t1, SZREG(t0)       // load next word
    addi    t0, t0, SZREG       // advance
    orc.b   t1, t1
    bgeu    t0, t4, 4f          // boundary check AFTER load

where t4 = (s + count) & -SZREG.  When s is aligned and count is a
multiple of SZREG, t4 equals s + count and the loop loads a full word
starting at exactly s + count.  If s + count falls on a page boundary
with the next page unmapped, this faults.

Fix by computing the aligned boundary from the last valid byte
(s + count - 1) instead of s + count.  This makes the loop stop at the
word containing the last valid byte rather than potentially loading the
word after it.  The count == 0 case is already handled by the beqz
early exit.

Also add a pre-loop guard (bgeu t0, t4) for the case where all valid
bytes fit within the first word.  With the adjusted boundary, t4 can
equal t0, and entering the loop with stale register state from the
first-word processing would produce incorrect results.

The final minu clamp ensures the result is still correct when the last
loaded word extends past s + count - 1 within the same aligned word.

Fixes: 5ba15d419f ("riscv: lib: add strnlen() implementation")
Signed-off-by: Michael Neuling <mikey@neuling.org>
Assisted-by: Claude Opus4.6 High Thinking
Link: https://patch.msgid.link/20260413010738.1622423-1-mikey@neuling.org
Signed-off-by: Paul Walmsley <pjw@kernel.org>
History 2026-08-08 11:45:33 -06:00
..
ashldi3.S riscv: add platform-specific double word shifts for riscv32 2026-05-28 21:24:51 -07:00
ashrdi3.S riscv: add platform-specific double word shifts for riscv32 2026-05-28 21:24:51 -07:00
clear_page.S use linux/export.h rather than asm-generic/export.h 2024-01-09 20:10:40 -08:00
csum.c riscv: fix various typos in comments and code 2026-04-04 18:42:39 -06:00
delay.c include/linux/delay.h: replace kernel.h with the necessary inclusions 2021-11-09 10:02:49 -08:00
error-inject.c riscv: Add support for function error injection 2021-01-14 15:09:09 -08:00
lshrdi3.S riscv: add platform-specific double word shifts for riscv32 2026-05-28 21:24:51 -07:00
Makefile riscv: add platform-specific double word shifts for riscv32 2026-05-28 21:24:51 -07:00
memcpy.S riscv: Use SYM_*() assembly macros instead of deprecated ones 2023-11-06 09:42:47 -08:00
memmove.S riscv: fix various typos in comments and code 2026-04-04 18:42:39 -06:00
memset.S RISC-V: lib: Add pi aliases for string functions 2024-08-05 12:06:39 -07:00
riscv_v_helpers.c riscv: make unsafe user copy routines use existing assembly routines 2025-06-05 11:39:15 -07:00
strchr.S riscv: lib: add strchr() implementation 2026-04-04 18:42:44 -06:00
strcmp.S RISC-V: separate Zbb optimisations requiring and not requiring toolchain support 2025-03-18 08:53:02 +00:00
strlen.S riscv: lib: optimize strlen loop efficiency 2026-02-09 15:27:33 -07:00
strncmp.S RISC-V: separate Zbb optimisations requiring and not requiring toolchain support 2025-03-18 08:53:02 +00:00
strnlen.S riscv: lib: Fix ZBB strnlen reading past count boundary 2026-08-08 11:45:33 -06:00
strrchr.S riscv: lib: add strrchr() implementation 2026-04-04 18:42:44 -06:00
tishift.S use linux/export.h rather than asm-generic/export.h 2024-01-09 20:10:40 -08:00
uaccess.S riscv: make unsafe user copy routines use existing assembly routines 2025-06-05 11:39:15 -07:00
uaccess_vector.S riscv: make unsafe user copy routines use existing assembly routines 2025-06-05 11:39:15 -07:00