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7182777666
On i.MX8MQ, the MIPI CSI reset lines are active-low and not self-clearing. Writing '0' asserts reset and it remains asserted until explicitly deasserted by software. This driver previously treated the MIPI CSI reset signals as active-high, which led to incorrect reset assert/deassert sequencing. This issue was exposed by commit6d79bb8fd2("media: imx8mq-mipi-csi2: Explicitly release reset"). Fix this by reflecting the correct reset polarity and ensuring proper reset handling. Fixes:c979dbf599("reset: imx7: Add support for i.MX8MQ IP block variant") Cc: stable@vger.kernel.org #6d79bb8fd2: media: imx8mq-mipi-csi2: Explicitly release reset Reviewed-by: Philipp Zabel <p.zabel@pengutronix.de> Signed-off-by: Robby Cai <robby.cai@nxp.com> Reviewed-by: Guoniu Zhou <guoniu.zhou@oss.nxp.com> Reviewed-by: Frank Li <Frank.Li@nxp.com> Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
413 lines
14 KiB
413 lines
14 KiB