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linux/drivers/spi/spi-amd.c

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spi: spi-amd: Add AMD SPI controller driver support This driver supports SPI Controller for AMD SOCs.This driver supports SPI operations using FIFO mode of transfer. Signed-off-by: Sanjay R Mehta <sanju.mehta@amd.com> Signed-off-by: Mark Brown <broonie@kernel.org> Link: https://lore.kernel.org/r/1587844788-33997-1-git-send-email-sanju.mehta@amd.com Signed-off-by: Mark Brown <broonie@kernel.org>
2020-04-25 14:59:48 -05:00
spi: spi_amd: Sort headers alphabetically Sorting headers alphabetically helps locating duplicates, and makes it easier to figure out where to insert new headers. Co-developed-by: Akshata MukundShetty <akshata.mukundshetty@amd.com> Signed-off-by: Akshata MukundShetty <akshata.mukundshetty@amd.com> Signed-off-by: Raju Rangoju <Raju.Rangoju@amd.com> Link: https://patch.msgid.link/20240925133644.2922359-2-Raju.Rangoju@amd.com Signed-off-by: Mark Brown <broonie@kernel.org>
2024-09-25 19:06:37 +05:30
spi: spi_amd: Add HIDDMA basic read support SPI index mode has hardware limitation of reading only 64 bytes per transaction due to fixed number of FIFO registers. This constraint leads to performance issues when reading data from NAND/NOR flash devices, as the controller must issue multiple requests to read 64-byte chunks, even if the slave can send up to 2 or 4 KB in single transaction. The AMD HID2 SPI controller supports DMA mode, which allows reading up to 4 KB of data in single transaction. This patch introduces changes to implement HID2 DMA read support for the HID2 SPI controller. Co-developed-by: Krishnamoorthi M <krishnamoorthi.m@amd.com> Signed-off-by: Krishnamoorthi M <krishnamoorthi.m@amd.com> Co-developed-by: Akshata MukundShetty <akshata.mukundshetty@amd.com> Signed-off-by: Akshata MukundShetty <akshata.mukundshetty@amd.com> Signed-off-by: Raju Rangoju <Raju.Rangoju@amd.com> Link: https://patch.msgid.link/20240925133644.2922359-9-Raju.Rangoju@amd.com Signed-off-by: Mark Brown <broonie@kernel.org>
2024-09-25 19:06:44 +05:30
spi: spi-amd: Add AMD SPI controller driver support This driver supports SPI Controller for AMD SOCs.This driver supports SPI operations using FIFO mode of transfer. Signed-off-by: Sanjay R Mehta <sanju.mehta@amd.com> Signed-off-by: Mark Brown <broonie@kernel.org> Link: https://lore.kernel.org/r/1587844788-33997-1-git-send-email-sanju.mehta@amd.com Signed-off-by: Mark Brown <broonie@kernel.org>
2020-04-25 14:59:48 -05:00
spi: spi_amd: Optimize IO operations Read and write the maximum number of data bytes at once, rather than byte by byte. This improves AMD SPI controller driver performance by reducing the time required to access FIFO registers. For example, with the new changes, 64 bytes of data from the FIFO queue can be read in 8 read calls (8 bytes per call) instead of 64 read calls(1 byte per call). Co-developed-by: Krishnamoorthi M <krishnamoorthi.m@amd.com> Signed-off-by: Krishnamoorthi M <krishnamoorthi.m@amd.com> Co-developed-by: Akshata MukundShetty <akshata.mukundshetty@amd.com> Signed-off-by: Akshata MukundShetty <akshata.mukundshetty@amd.com> Signed-off-by: Raju Rangoju <Raju.Rangoju@amd.com> Link: https://patch.msgid.link/20240925133644.2922359-6-Raju.Rangoju@amd.com Signed-off-by: Mark Brown <broonie@kernel.org>
2024-09-25 19:06:41 +05:30
spi: spi_amd: Sort headers alphabetically Sorting headers alphabetically helps locating duplicates, and makes it easier to figure out where to insert new headers. Co-developed-by: Akshata MukundShetty <akshata.mukundshetty@amd.com> Signed-off-by: Akshata MukundShetty <akshata.mukundshetty@amd.com> Signed-off-by: Raju Rangoju <Raju.Rangoju@amd.com> Link: https://patch.msgid.link/20240925133644.2922359-2-Raju.Rangoju@amd.com Signed-off-by: Mark Brown <broonie@kernel.org>
2024-09-25 19:06:37 +05:30
spi: spi-amd: Add AMD SPI controller driver support This driver supports SPI Controller for AMD SOCs.This driver supports SPI operations using FIFO mode of transfer. Signed-off-by: Sanjay R Mehta <sanju.mehta@amd.com> Signed-off-by: Mark Brown <broonie@kernel.org> Link: https://lore.kernel.org/r/1587844788-33997-1-git-send-email-sanju.mehta@amd.com Signed-off-by: Mark Brown <broonie@kernel.org>
2020-04-25 14:59:48 -05:00
spi: spi_amd: Add support for SPI MEM framework Add support to the SPI controller driver to use SPI MEM framework. SPI subsystem utilizing the SPI memory operations allows to re-use SPI controller drivers for both SPI NOR devices, regular SPI devices as well as SPI NAND devices. Add below functions of spi_mem_ops to support SPI MEM framework - exec-op(): to execute the memory operations. - supports_op(): to check if the memory operation is supported. - adjust_op_size(): to split data transfers so that they don’t exceed the max transfer size supported by the controller. Suggested-by: Sudheesh Mavila <sudheesh.mavila@amd.com> Co-developed-by: Krishnamoorthi M <krishnamoorthi.m@amd.com> Signed-off-by: Krishnamoorthi M <krishnamoorthi.m@amd.com> Co-developed-by: Akshata MukundShetty <akshata.mukundshetty@amd.com> Signed-off-by: Akshata MukundShetty <akshata.mukundshetty@amd.com> Signed-off-by: Raju Rangoju <Raju.Rangoju@amd.com> Link: https://msgid.link/r/20240229134544.3461757-1-Raju.Rangoju@amd.com Signed-off-by: Mark Brown <broonie@kernel.org>
2024-02-29 19:15:44 +05:30
spi: spi-amd: Add AMD SPI controller driver support This driver supports SPI Controller for AMD SOCs.This driver supports SPI operations using FIFO mode of transfer. Signed-off-by: Sanjay R Mehta <sanju.mehta@amd.com> Signed-off-by: Mark Brown <broonie@kernel.org> Link: https://lore.kernel.org/r/1587844788-33997-1-git-send-email-sanju.mehta@amd.com Signed-off-by: Mark Brown <broonie@kernel.org>
2020-04-25 14:59:48 -05:00
spi: spi_amd: Add PCI-based driver for AMD HID2 SPI controller Register a new driver(spi_amd_pci) for the HID2 SPI controller using the PCI ID of the LPC bridge device. Add a new common probe function in spi_amd driver to encapsulate the code required for registering the controller driver. This function will be utilized by both the existing ACPI driver and the newly introduced PCI-based driver for the HID2 SPI controller. The MMIO register base address of the HID2 SPI controller can be obtained from the PCI LPC bridge registers. By implementing these changes, the DMA buffer will be correctly associated with the LPC bridge device, preventing IO_PAGE_FAULT caused by IOMMU when the LPC bridge attempts DMA operations on addresses owned by the HID2 SPI controller. Co-developed-by: Krishnamoorthi M <krishnamoorthi.m@amd.com> Signed-off-by: Krishnamoorthi M <krishnamoorthi.m@amd.com> Co-developed-by: Akshata MukundShetty <akshata.mukundshetty@amd.com> Signed-off-by: Akshata MukundShetty <akshata.mukundshetty@amd.com> Signed-off-by: Raju Rangoju <Raju.Rangoju@amd.com> Link: https://patch.msgid.link/20250402121514.2941334-1-Raju.Rangoju@amd.com Signed-off-by: Mark Brown <broonie@kernel.org>
2025-04-02 17:45:14 +05:30
spi: spi-amd: Add AMD SPI controller driver support This driver supports SPI Controller for AMD SOCs.This driver supports SPI operations using FIFO mode of transfer. Signed-off-by: Sanjay R Mehta <sanju.mehta@amd.com> Signed-off-by: Mark Brown <broonie@kernel.org> Link: https://lore.kernel.org/r/1587844788-33997-1-git-send-email-sanju.mehta@amd.com Signed-off-by: Mark Brown <broonie@kernel.org>
2020-04-25 14:59:48 -05:00
spi: amd: Add support for version AMDI0062 Add support for the AMD SPI controller version AMDI0062. Do this in a modular way where's easy to add new versions. Signed-off-by: André Almeida <andrealmeid@collabora.com> Link: https://lore.kernel.org/r/20220211143155.75513-4-andrealmeid@collabora.com Signed-off-by: Mark Brown <broonie@kernel.org>
2022-02-11 11:31:55 -03:00
spi: spi-amd: Add AMD SPI controller driver support This driver supports SPI Controller for AMD SOCs.This driver supports SPI operations using FIFO mode of transfer. Signed-off-by: Sanjay R Mehta <sanju.mehta@amd.com> Signed-off-by: Mark Brown <broonie@kernel.org> Link: https://lore.kernel.org/r/1587844788-33997-1-git-send-email-sanju.mehta@amd.com Signed-off-by: Mark Brown <broonie@kernel.org>
2020-04-25 14:59:48 -05:00
spi: spi_amd: Set controller address mode Add changes to set the controller address mode before initiating commands. The AMD SPI0 controller(AMDI0062) supports both 24-bit and 32-bit address modes, while the HID2 SPI controller(AMDI0063) supports only the 24-bit address mode. So this change is applicable only for SPI0 controller. Co-developed-by: Krishnamoorthi M <krishnamoorthi.m@amd.com> Signed-off-by: Krishnamoorthi M <krishnamoorthi.m@amd.com> Co-developed-by: Akshata MukundShetty <akshata.mukundshetty@amd.com> Signed-off-by: Akshata MukundShetty <akshata.mukundshetty@amd.com> Signed-off-by: Raju Rangoju <Raju.Rangoju@amd.com> Link: https://patch.msgid.link/20240925133644.2922359-8-Raju.Rangoju@amd.com Signed-off-by: Mark Brown <broonie@kernel.org>
2024-09-25 19:06:43 +05:30
spi: spi-amd: Add AMD SPI controller driver support This driver supports SPI Controller for AMD SOCs.This driver supports SPI operations using FIFO mode of transfer. Signed-off-by: Sanjay R Mehta <sanju.mehta@amd.com> Signed-off-by: Mark Brown <broonie@kernel.org> Link: https://lore.kernel.org/r/1587844788-33997-1-git-send-email-sanju.mehta@amd.com Signed-off-by: Mark Brown <broonie@kernel.org>
2020-04-25 14:59:48 -05:00
spi: amd: Limit max transfer and message size Enabling the SPI CS35L41 audio codec driver for Steam Deck [1] revealed a problem with the current AMD SPI controller driver implementation, consisting of an unrecoverable system hang. The issue can be prevented if we ensure the max transfer size and the max message size do not exceed the FIFO buffer size. According to the implementation of the downstream driver, the AMD SPI controller is not able to handle more than 70 bytes per transfer, which corresponds to the size of the FIFO buffer. Hence, let's fix this by setting the SPI limits mentioned above. [1] https://lore.kernel.org/r/20220621213819.262537-1-cristian.ciocaltea@collabora.com Reported-by: Anastasios Vacharakis <vacharakis@o2mail.de> Fixes: bbb336f39efc ("spi: spi-amd: Add AMD SPI controller driver support") Signed-off-by: Cristian Ciocaltea <cristian.ciocaltea@collabora.com> Link: https://lore.kernel.org/r/20220706100626.1234731-2-cristian.ciocaltea@collabora.com Signed-off-by: Mark Brown <broonie@kernel.org>
2022-07-06 13:06:22 +03:00
spi: spi-amd: Add AMD SPI controller driver support This driver supports SPI Controller for AMD SOCs.This driver supports SPI operations using FIFO mode of transfer. Signed-off-by: Sanjay R Mehta <sanju.mehta@amd.com> Signed-off-by: Mark Brown <broonie@kernel.org> Link: https://lore.kernel.org/r/1587844788-33997-1-git-send-email-sanju.mehta@amd.com Signed-off-by: Mark Brown <broonie@kernel.org>
2020-04-25 14:59:48 -05:00
spi: spi_amd: Add support for SPI MEM framework Add support to the SPI controller driver to use SPI MEM framework. SPI subsystem utilizing the SPI memory operations allows to re-use SPI controller drivers for both SPI NOR devices, regular SPI devices as well as SPI NAND devices. Add below functions of spi_mem_ops to support SPI MEM framework - exec-op(): to execute the memory operations. - supports_op(): to check if the memory operation is supported. - adjust_op_size(): to split data transfers so that they don’t exceed the max transfer size supported by the controller. Suggested-by: Sudheesh Mavila <sudheesh.mavila@amd.com> Co-developed-by: Krishnamoorthi M <krishnamoorthi.m@amd.com> Signed-off-by: Krishnamoorthi M <krishnamoorthi.m@amd.com> Co-developed-by: Akshata MukundShetty <akshata.mukundshetty@amd.com> Signed-off-by: Akshata MukundShetty <akshata.mukundshetty@amd.com> Signed-off-by: Raju Rangoju <Raju.Rangoju@amd.com> Link: https://msgid.link/r/20240229134544.3461757-1-Raju.Rangoju@amd.com Signed-off-by: Mark Brown <broonie@kernel.org>
2024-02-29 19:15:44 +05:30
spi: spi_amd: Add support for HID2 SPI controller AMD SoC has HID2 SPI controller in addition to the existing SPI0 controller(AMDI0062). Add HID2 SPI controller's ACPI ID AMDI0063 with its version ID to the list of supported devices. Use the version ID to differentiate the register offsets. And, the AMD HID2 SPI controller supports DMA read, allowing for up to 4 KB of data to be read in single transaction. Update the SPI-MEM support function to reflect this capability. Co-developed-by: Krishnamoorthi M <krishnamoorthi.m@amd.com> Signed-off-by: Krishnamoorthi M <krishnamoorthi.m@amd.com> Co-developed-by: Akshata MukundShetty <akshata.mukundshetty@amd.com> Signed-off-by: Akshata MukundShetty <akshata.mukundshetty@amd.com> Signed-off-by: Raju Rangoju <Raju.Rangoju@amd.com> Link: https://patch.msgid.link/20240925133644.2922359-7-Raju.Rangoju@amd.com Signed-off-by: Mark Brown <broonie@kernel.org>
2024-09-25 19:06:42 +05:30
spi: spi-amd: Add AMD SPI controller driver support This driver supports SPI Controller for AMD SOCs.This driver supports SPI operations using FIFO mode of transfer. Signed-off-by: Sanjay R Mehta <sanju.mehta@amd.com> Signed-off-by: Mark Brown <broonie@kernel.org> Link: https://lore.kernel.org/r/1587844788-33997-1-git-send-email-sanju.mehta@amd.com Signed-off-by: Mark Brown <broonie@kernel.org>
2020-04-25 14:59:48 -05:00
spi: amd: Configure device speed Number of clock frequencies are supported by AMD controller which are mentioned in the amd_spi_freq structure table. Create mechanism to configure device clock frequency such that it is strictly less than the requested frequency. Give priority to the device transfer speed and in case it is not set then use the max clock speed supported by the device. Signed-off-by: Lucas Tanure <tanureal@opensource.cirrus.com> Co-developed-by: Shreeya Patel <shreeya.patel@collabora.com> Signed-off-by: Shreeya Patel <shreeya.patel@collabora.com> Link: https://lore.kernel.org/r/20220825143132.253224-1-shreeya.patel@collabora.com Signed-off-by: Mark Brown <broonie@kernel.org>
2022-08-25 20:01:32 +05:30
spi: spi_amd: Add HIDDMA basic read support SPI index mode has hardware limitation of reading only 64 bytes per transaction due to fixed number of FIFO registers. This constraint leads to performance issues when reading data from NAND/NOR flash devices, as the controller must issue multiple requests to read 64-byte chunks, even if the slave can send up to 2 or 4 KB in single transaction. The AMD HID2 SPI controller supports DMA mode, which allows reading up to 4 KB of data in single transaction. This patch introduces changes to implement HID2 DMA read support for the HID2 SPI controller. Co-developed-by: Krishnamoorthi M <krishnamoorthi.m@amd.com> Signed-off-by: Krishnamoorthi M <krishnamoorthi.m@amd.com> Co-developed-by: Akshata MukundShetty <akshata.mukundshetty@amd.com> Signed-off-by: Akshata MukundShetty <akshata.mukundshetty@amd.com> Signed-off-by: Raju Rangoju <Raju.Rangoju@amd.com> Link: https://patch.msgid.link/20240925133644.2922359-9-Raju.Rangoju@amd.com Signed-off-by: Mark Brown <broonie@kernel.org>
2024-09-25 19:06:44 +05:30
spi: spi_amd: Add HIDDMA basic write support SPI index mode has hardware limitation of transferring only 64 bytes per transaction due to fixed number of FIFO registers. This constraint leads to performance issues when reading/writing data to/from NAND/NOR flash devices, as the controller must issue multiple requests to read/write 64-byte chunks, even if the slave can transfer up to 2 or 4 KB in a single transaction. The AMD HID2 SPI controller supports DMA mode, allowing for reading/writing up to 4 KB of data in a single transaction. The existing spi_amd driver already supports HID2 DMA read operations. This patch introduces changes to implement HID2 DMA single mode basic write support for the HID2 SPI controller. Co-developed-by: Krishnamoorthi M <krishnamoorthi.m@amd.com> Signed-off-by: Krishnamoorthi M <krishnamoorthi.m@amd.com> Co-developed-by: Akshata MukundShetty <akshata.mukundshetty@amd.com> Signed-off-by: Akshata MukundShetty <akshata.mukundshetty@amd.com> Signed-off-by: Raju Rangoju <Raju.Rangoju@amd.com> Link: https://patch.msgid.link/20250516100658.585654-3-Raju.Rangoju@amd.com Signed-off-by: Mark Brown <broonie@kernel.org>
2025-05-16 15:36:57 +05:30
spi: spi_amd: Add HIDDMA basic read support SPI index mode has hardware limitation of reading only 64 bytes per transaction due to fixed number of FIFO registers. This constraint leads to performance issues when reading data from NAND/NOR flash devices, as the controller must issue multiple requests to read 64-byte chunks, even if the slave can send up to 2 or 4 KB in single transaction. The AMD HID2 SPI controller supports DMA mode, which allows reading up to 4 KB of data in single transaction. This patch introduces changes to implement HID2 DMA read support for the HID2 SPI controller. Co-developed-by: Krishnamoorthi M <krishnamoorthi.m@amd.com> Signed-off-by: Krishnamoorthi M <krishnamoorthi.m@amd.com> Co-developed-by: Akshata MukundShetty <akshata.mukundshetty@amd.com> Signed-off-by: Akshata MukundShetty <akshata.mukundshetty@amd.com> Signed-off-by: Raju Rangoju <Raju.Rangoju@amd.com> Link: https://patch.msgid.link/20240925133644.2922359-9-Raju.Rangoju@amd.com Signed-off-by: Mark Brown <broonie@kernel.org>
2024-09-25 19:06:44 +05:30
spi: spi_amd: Add HIDDMA basic write support SPI index mode has hardware limitation of transferring only 64 bytes per transaction due to fixed number of FIFO registers. This constraint leads to performance issues when reading/writing data to/from NAND/NOR flash devices, as the controller must issue multiple requests to read/write 64-byte chunks, even if the slave can transfer up to 2 or 4 KB in a single transaction. The AMD HID2 SPI controller supports DMA mode, allowing for reading/writing up to 4 KB of data in a single transaction. The existing spi_amd driver already supports HID2 DMA read operations. This patch introduces changes to implement HID2 DMA single mode basic write support for the HID2 SPI controller. Co-developed-by: Krishnamoorthi M <krishnamoorthi.m@amd.com> Signed-off-by: Krishnamoorthi M <krishnamoorthi.m@amd.com> Co-developed-by: Akshata MukundShetty <akshata.mukundshetty@amd.com> Signed-off-by: Akshata MukundShetty <akshata.mukundshetty@amd.com> Signed-off-by: Raju Rangoju <Raju.Rangoju@amd.com> Link: https://patch.msgid.link/20250516100658.585654-3-Raju.Rangoju@amd.com Signed-off-by: Mark Brown <broonie@kernel.org>
2025-05-16 15:36:57 +05:30
spi: spi_amd: Add HIDDMA basic read support SPI index mode has hardware limitation of reading only 64 bytes per transaction due to fixed number of FIFO registers. This constraint leads to performance issues when reading data from NAND/NOR flash devices, as the controller must issue multiple requests to read 64-byte chunks, even if the slave can send up to 2 or 4 KB in single transaction. The AMD HID2 SPI controller supports DMA mode, which allows reading up to 4 KB of data in single transaction. This patch introduces changes to implement HID2 DMA read support for the HID2 SPI controller. Co-developed-by: Krishnamoorthi M <krishnamoorthi.m@amd.com> Signed-off-by: Krishnamoorthi M <krishnamoorthi.m@amd.com> Co-developed-by: Akshata MukundShetty <akshata.mukundshetty@amd.com> Signed-off-by: Akshata MukundShetty <akshata.mukundshetty@amd.com> Signed-off-by: Raju Rangoju <Raju.Rangoju@amd.com> Link: https://patch.msgid.link/20240925133644.2922359-9-Raju.Rangoju@amd.com Signed-off-by: Mark Brown <broonie@kernel.org>
2024-09-25 19:06:44 +05:30
spi: amd: Configure device speed Number of clock frequencies are supported by AMD controller which are mentioned in the amd_spi_freq structure table. Create mechanism to configure device clock frequency such that it is strictly less than the requested frequency. Give priority to the device transfer speed and in case it is not set then use the max clock speed supported by the device. Signed-off-by: Lucas Tanure <tanureal@opensource.cirrus.com> Co-developed-by: Shreeya Patel <shreeya.patel@collabora.com> Signed-off-by: Shreeya Patel <shreeya.patel@collabora.com> Link: https://lore.kernel.org/r/20220825143132.253224-1-shreeya.patel@collabora.com Signed-off-by: Mark Brown <broonie@kernel.org>
2022-08-25 20:01:32 +05:30
spi: spi_amd: Add HIDDMA basic read support SPI index mode has hardware limitation of reading only 64 bytes per transaction due to fixed number of FIFO registers. This constraint leads to performance issues when reading data from NAND/NOR flash devices, as the controller must issue multiple requests to read 64-byte chunks, even if the slave can send up to 2 or 4 KB in single transaction. The AMD HID2 SPI controller supports DMA mode, which allows reading up to 4 KB of data in single transaction. This patch introduces changes to implement HID2 DMA read support for the HID2 SPI controller. Co-developed-by: Krishnamoorthi M <krishnamoorthi.m@amd.com> Signed-off-by: Krishnamoorthi M <krishnamoorthi.m@amd.com> Co-developed-by: Akshata MukundShetty <akshata.mukundshetty@amd.com> Signed-off-by: Akshata MukundShetty <akshata.mukundshetty@amd.com> Signed-off-by: Raju Rangoju <Raju.Rangoju@amd.com> Link: https://patch.msgid.link/20240925133644.2922359-9-Raju.Rangoju@amd.com Signed-off-by: Mark Brown <broonie@kernel.org>
2024-09-25 19:06:44 +05:30
spi: spi_amd: Enable dual and quad I/O modes The current spi_amd driver only supports single I/O mode, despite the AMD SPI controller's capability for dual and quad I/O modes for read operations. And AMD SPI0 controller has limited support for quad mode write operations. Update the SPI-MEM support function to reflect these hardware capabilities. Co-developed-by: Krishnamoorthi M <krishnamoorthi.m@amd.com> Signed-off-by: Krishnamoorthi M <krishnamoorthi.m@amd.com> Co-developed-by: Akshata MukundShetty <akshata.mukundshetty@amd.com> Signed-off-by: Akshata MukundShetty <akshata.mukundshetty@amd.com> Signed-off-by: Raju Rangoju <Raju.Rangoju@amd.com> Link: https://patch.msgid.link/20240925133644.2922359-3-Raju.Rangoju@amd.com Signed-off-by: Mark Brown <broonie@kernel.org>
2024-09-25 19:06:38 +05:30
spi: spi_amd: Add HIDDMA basic write support SPI index mode has hardware limitation of transferring only 64 bytes per transaction due to fixed number of FIFO registers. This constraint leads to performance issues when reading/writing data to/from NAND/NOR flash devices, as the controller must issue multiple requests to read/write 64-byte chunks, even if the slave can transfer up to 2 or 4 KB in a single transaction. The AMD HID2 SPI controller supports DMA mode, allowing for reading/writing up to 4 KB of data in a single transaction. The existing spi_amd driver already supports HID2 DMA read operations. This patch introduces changes to implement HID2 DMA single mode basic write support for the HID2 SPI controller. Co-developed-by: Krishnamoorthi M <krishnamoorthi.m@amd.com> Signed-off-by: Krishnamoorthi M <krishnamoorthi.m@amd.com> Co-developed-by: Akshata MukundShetty <akshata.mukundshetty@amd.com> Signed-off-by: Akshata MukundShetty <akshata.mukundshetty@amd.com> Signed-off-by: Raju Rangoju <Raju.Rangoju@amd.com> Link: https://patch.msgid.link/20250516100658.585654-3-Raju.Rangoju@amd.com Signed-off-by: Mark Brown <broonie@kernel.org>
2025-05-16 15:36:57 +05:30
spi: amd: Configure device speed Number of clock frequencies are supported by AMD controller which are mentioned in the amd_spi_freq structure table. Create mechanism to configure device clock frequency such that it is strictly less than the requested frequency. Give priority to the device transfer speed and in case it is not set then use the max clock speed supported by the device. Signed-off-by: Lucas Tanure <tanureal@opensource.cirrus.com> Co-developed-by: Shreeya Patel <shreeya.patel@collabora.com> Signed-off-by: Shreeya Patel <shreeya.patel@collabora.com> Link: https://lore.kernel.org/r/20220825143132.253224-1-shreeya.patel@collabora.com Signed-off-by: Mark Brown <broonie@kernel.org>
2022-08-25 20:01:32 +05:30
spi: amd: Fix SPI_SPD7 value According to data sheet SPI_SPD7 should be set to 7. Signed-off-by: Vitaly Rodionov <vitalyr@opensource.cirrus.com> Link: https://lore.kernel.org/r/20221104100637.13376-1-vitalyr@opensource.cirrus.com Signed-off-by: Mark Brown <broonie@kernel.org>
2022-11-04 10:06:37 +00:00
spi: amd: Configure device speed Number of clock frequencies are supported by AMD controller which are mentioned in the amd_spi_freq structure table. Create mechanism to configure device clock frequency such that it is strictly less than the requested frequency. Give priority to the device transfer speed and in case it is not set then use the max clock speed supported by the device. Signed-off-by: Lucas Tanure <tanureal@opensource.cirrus.com> Co-developed-by: Shreeya Patel <shreeya.patel@collabora.com> Signed-off-by: Shreeya Patel <shreeya.patel@collabora.com> Link: https://lore.kernel.org/r/20220825143132.253224-1-shreeya.patel@collabora.com Signed-off-by: Mark Brown <broonie@kernel.org>
2022-08-25 20:01:32 +05:30
spi: amd: Refactor code to use less spi_master_get_devdata Get master data in the start and then just use struct amd_spi as it has the needed variable Signed-off-by: Lucas Tanure <tanureal@opensource.cirrus.com> Reviewed-by: Charles Keepax <ckeepax@opensource.cirrus.com> Link: https://lore.kernel.org/r/20210910111529.12539-1-tanureal@opensource.cirrus.com Signed-off-by: Mark Brown <broonie@kernel.org>
2021-09-10 12:15:26 +01:00
spi: spi-amd: Add AMD SPI controller driver support This driver supports SPI Controller for AMD SOCs.This driver supports SPI operations using FIFO mode of transfer. Signed-off-by: Sanjay R Mehta <sanju.mehta@amd.com> Signed-off-by: Mark Brown <broonie@kernel.org> Link: https://lore.kernel.org/r/1587844788-33997-1-git-send-email-sanju.mehta@amd.com Signed-off-by: Mark Brown <broonie@kernel.org>
2020-04-25 14:59:48 -05:00
spi: spi_amd: Replace ioread/iowrite calls All `ioread*` and `iowrite*` functions are better suited for architecture independent code to ensure portability across different architectures. Since AMD SoCs support only the x86 architecture, replacing all `ioread*` and `iowrite*` calls with `read*` and `write*` calls can reduce the overhead of ensuring portability and increase the speed of I/O operations. Co-developed-by: Krishnamoorthi M <krishnamoorthi.m@amd.com> Signed-off-by: Krishnamoorthi M <krishnamoorthi.m@amd.com> Co-developed-by: Akshata MukundShetty <akshata.mukundshetty@amd.com> Signed-off-by: Akshata MukundShetty <akshata.mukundshetty@amd.com> Signed-off-by: Raju Rangoju <Raju.Rangoju@amd.com> Link: https://patch.msgid.link/20240925133644.2922359-4-Raju.Rangoju@amd.com Signed-off-by: Mark Brown <broonie@kernel.org>
2024-09-25 19:06:39 +05:30
spi: spi-amd: Add AMD SPI controller driver support This driver supports SPI Controller for AMD SOCs.This driver supports SPI operations using FIFO mode of transfer. Signed-off-by: Sanjay R Mehta <sanju.mehta@amd.com> Signed-off-by: Mark Brown <broonie@kernel.org> Link: https://lore.kernel.org/r/1587844788-33997-1-git-send-email-sanju.mehta@amd.com Signed-off-by: Mark Brown <broonie@kernel.org>
2020-04-25 14:59:48 -05:00
spi: amd: Refactor code to use less spi_master_get_devdata Get master data in the start and then just use struct amd_spi as it has the needed variable Signed-off-by: Lucas Tanure <tanureal@opensource.cirrus.com> Reviewed-by: Charles Keepax <ckeepax@opensource.cirrus.com> Link: https://lore.kernel.org/r/20210910111529.12539-1-tanureal@opensource.cirrus.com Signed-off-by: Mark Brown <broonie@kernel.org>
2021-09-10 12:15:26 +01:00
spi: spi-amd: Add AMD SPI controller driver support This driver supports SPI Controller for AMD SOCs.This driver supports SPI operations using FIFO mode of transfer. Signed-off-by: Sanjay R Mehta <sanju.mehta@amd.com> Signed-off-by: Mark Brown <broonie@kernel.org> Link: https://lore.kernel.org/r/1587844788-33997-1-git-send-email-sanju.mehta@amd.com Signed-off-by: Mark Brown <broonie@kernel.org>
2020-04-25 14:59:48 -05:00
spi: spi_amd: Replace ioread/iowrite calls All `ioread*` and `iowrite*` functions are better suited for architecture independent code to ensure portability across different architectures. Since AMD SoCs support only the x86 architecture, replacing all `ioread*` and `iowrite*` calls with `read*` and `write*` calls can reduce the overhead of ensuring portability and increase the speed of I/O operations. Co-developed-by: Krishnamoorthi M <krishnamoorthi.m@amd.com> Signed-off-by: Krishnamoorthi M <krishnamoorthi.m@amd.com> Co-developed-by: Akshata MukundShetty <akshata.mukundshetty@amd.com> Signed-off-by: Akshata MukundShetty <akshata.mukundshetty@amd.com> Signed-off-by: Raju Rangoju <Raju.Rangoju@amd.com> Link: https://patch.msgid.link/20240925133644.2922359-4-Raju.Rangoju@amd.com Signed-off-by: Mark Brown <broonie@kernel.org>
2024-09-25 19:06:39 +05:30
spi: spi-amd: Add AMD SPI controller driver support This driver supports SPI Controller for AMD SOCs.This driver supports SPI operations using FIFO mode of transfer. Signed-off-by: Sanjay R Mehta <sanju.mehta@amd.com> Signed-off-by: Mark Brown <broonie@kernel.org> Link: https://lore.kernel.org/r/1587844788-33997-1-git-send-email-sanju.mehta@amd.com Signed-off-by: Mark Brown <broonie@kernel.org>
2020-04-25 14:59:48 -05:00
spi: amd: Refactor code to use less spi_master_get_devdata Get master data in the start and then just use struct amd_spi as it has the needed variable Signed-off-by: Lucas Tanure <tanureal@opensource.cirrus.com> Reviewed-by: Charles Keepax <ckeepax@opensource.cirrus.com> Link: https://lore.kernel.org/r/20210910111529.12539-1-tanureal@opensource.cirrus.com Signed-off-by: Mark Brown <broonie@kernel.org>
2021-09-10 12:15:26 +01:00
spi: spi-amd: Add AMD SPI controller driver support This driver supports SPI Controller for AMD SOCs.This driver supports SPI operations using FIFO mode of transfer. Signed-off-by: Sanjay R Mehta <sanju.mehta@amd.com> Signed-off-by: Mark Brown <broonie@kernel.org> Link: https://lore.kernel.org/r/1587844788-33997-1-git-send-email-sanju.mehta@amd.com Signed-off-by: Mark Brown <broonie@kernel.org>
2020-04-25 14:59:48 -05:00
spi: amd: Refactor code to use less spi_master_get_devdata Get master data in the start and then just use struct amd_spi as it has the needed variable Signed-off-by: Lucas Tanure <tanureal@opensource.cirrus.com> Reviewed-by: Charles Keepax <ckeepax@opensource.cirrus.com> Link: https://lore.kernel.org/r/20210910111529.12539-1-tanureal@opensource.cirrus.com Signed-off-by: Mark Brown <broonie@kernel.org>
2021-09-10 12:15:26 +01:00
spi: spi-amd: Add AMD SPI controller driver support This driver supports SPI Controller for AMD SOCs.This driver supports SPI operations using FIFO mode of transfer. Signed-off-by: Sanjay R Mehta <sanju.mehta@amd.com> Signed-off-by: Mark Brown <broonie@kernel.org> Link: https://lore.kernel.org/r/1587844788-33997-1-git-send-email-sanju.mehta@amd.com Signed-off-by: Mark Brown <broonie@kernel.org>
2020-04-25 14:59:48 -05:00
spi: amd: Refactor code to use less spi_master_get_devdata Get master data in the start and then just use struct amd_spi as it has the needed variable Signed-off-by: Lucas Tanure <tanureal@opensource.cirrus.com> Reviewed-by: Charles Keepax <ckeepax@opensource.cirrus.com> Link: https://lore.kernel.org/r/20210910111529.12539-1-tanureal@opensource.cirrus.com Signed-off-by: Mark Brown <broonie@kernel.org>
2021-09-10 12:15:26 +01:00
spi: spi-amd: Add AMD SPI controller driver support This driver supports SPI Controller for AMD SOCs.This driver supports SPI operations using FIFO mode of transfer. Signed-off-by: Sanjay R Mehta <sanju.mehta@amd.com> Signed-off-by: Mark Brown <broonie@kernel.org> Link: https://lore.kernel.org/r/1587844788-33997-1-git-send-email-sanju.mehta@amd.com Signed-off-by: Mark Brown <broonie@kernel.org>
2020-04-25 14:59:48 -05:00
spi: spi_amd: Add HIDDMA basic read support SPI index mode has hardware limitation of reading only 64 bytes per transaction due to fixed number of FIFO registers. This constraint leads to performance issues when reading data from NAND/NOR flash devices, as the controller must issue multiple requests to read 64-byte chunks, even if the slave can send up to 2 or 4 KB in single transaction. The AMD HID2 SPI controller supports DMA mode, which allows reading up to 4 KB of data in single transaction. This patch introduces changes to implement HID2 DMA read support for the HID2 SPI controller. Co-developed-by: Krishnamoorthi M <krishnamoorthi.m@amd.com> Signed-off-by: Krishnamoorthi M <krishnamoorthi.m@amd.com> Co-developed-by: Akshata MukundShetty <akshata.mukundshetty@amd.com> Signed-off-by: Akshata MukundShetty <akshata.mukundshetty@amd.com> Signed-off-by: Raju Rangoju <Raju.Rangoju@amd.com> Link: https://patch.msgid.link/20240925133644.2922359-9-Raju.Rangoju@amd.com Signed-off-by: Mark Brown <broonie@kernel.org>
2024-09-25 19:06:44 +05:30
spi: amd: Refactor code to use less spi_master_get_devdata Get master data in the start and then just use struct amd_spi as it has the needed variable Signed-off-by: Lucas Tanure <tanureal@opensource.cirrus.com> Reviewed-by: Charles Keepax <ckeepax@opensource.cirrus.com> Link: https://lore.kernel.org/r/20210910111529.12539-1-tanureal@opensource.cirrus.com Signed-off-by: Mark Brown <broonie@kernel.org>
2021-09-10 12:15:26 +01:00
spi: spi-amd: Add AMD SPI controller driver support This driver supports SPI Controller for AMD SOCs.This driver supports SPI operations using FIFO mode of transfer. Signed-off-by: Sanjay R Mehta <sanju.mehta@amd.com> Signed-off-by: Mark Brown <broonie@kernel.org> Link: https://lore.kernel.org/r/1587844788-33997-1-git-send-email-sanju.mehta@amd.com Signed-off-by: Mark Brown <broonie@kernel.org>
2020-04-25 14:59:48 -05:00
spi: spi_amd: Replace ioread/iowrite calls All `ioread*` and `iowrite*` functions are better suited for architecture independent code to ensure portability across different architectures. Since AMD SoCs support only the x86 architecture, replacing all `ioread*` and `iowrite*` calls with `read*` and `write*` calls can reduce the overhead of ensuring portability and increase the speed of I/O operations. Co-developed-by: Krishnamoorthi M <krishnamoorthi.m@amd.com> Signed-off-by: Krishnamoorthi M <krishnamoorthi.m@amd.com> Co-developed-by: Akshata MukundShetty <akshata.mukundshetty@amd.com> Signed-off-by: Akshata MukundShetty <akshata.mukundshetty@amd.com> Signed-off-by: Raju Rangoju <Raju.Rangoju@amd.com> Link: https://patch.msgid.link/20240925133644.2922359-4-Raju.Rangoju@amd.com Signed-off-by: Mark Brown <broonie@kernel.org>
2024-09-25 19:06:39 +05:30
spi: spi-amd: Add AMD SPI controller driver support This driver supports SPI Controller for AMD SOCs.This driver supports SPI operations using FIFO mode of transfer. Signed-off-by: Sanjay R Mehta <sanju.mehta@amd.com> Signed-off-by: Mark Brown <broonie@kernel.org> Link: https://lore.kernel.org/r/1587844788-33997-1-git-send-email-sanju.mehta@amd.com Signed-off-by: Mark Brown <broonie@kernel.org>
2020-04-25 14:59:48 -05:00
spi: amd: Refactor code to use less spi_master_get_devdata Get master data in the start and then just use struct amd_spi as it has the needed variable Signed-off-by: Lucas Tanure <tanureal@opensource.cirrus.com> Reviewed-by: Charles Keepax <ckeepax@opensource.cirrus.com> Link: https://lore.kernel.org/r/20210910111529.12539-1-tanureal@opensource.cirrus.com Signed-off-by: Mark Brown <broonie@kernel.org>
2021-09-10 12:15:26 +01:00
spi: spi-amd: Add AMD SPI controller driver support This driver supports SPI Controller for AMD SOCs.This driver supports SPI operations using FIFO mode of transfer. Signed-off-by: Sanjay R Mehta <sanju.mehta@amd.com> Signed-off-by: Mark Brown <broonie@kernel.org> Link: https://lore.kernel.org/r/1587844788-33997-1-git-send-email-sanju.mehta@amd.com Signed-off-by: Mark Brown <broonie@kernel.org>
2020-04-25 14:59:48 -05:00
spi: spi_amd: Replace ioread/iowrite calls All `ioread*` and `iowrite*` functions are better suited for architecture independent code to ensure portability across different architectures. Since AMD SoCs support only the x86 architecture, replacing all `ioread*` and `iowrite*` calls with `read*` and `write*` calls can reduce the overhead of ensuring portability and increase the speed of I/O operations. Co-developed-by: Krishnamoorthi M <krishnamoorthi.m@amd.com> Signed-off-by: Krishnamoorthi M <krishnamoorthi.m@amd.com> Co-developed-by: Akshata MukundShetty <akshata.mukundshetty@amd.com> Signed-off-by: Akshata MukundShetty <akshata.mukundshetty@amd.com> Signed-off-by: Raju Rangoju <Raju.Rangoju@amd.com> Link: https://patch.msgid.link/20240925133644.2922359-4-Raju.Rangoju@amd.com Signed-off-by: Mark Brown <broonie@kernel.org>
2024-09-25 19:06:39 +05:30
spi: spi-amd: Add AMD SPI controller driver support This driver supports SPI Controller for AMD SOCs.This driver supports SPI operations using FIFO mode of transfer. Signed-off-by: Sanjay R Mehta <sanju.mehta@amd.com> Signed-off-by: Mark Brown <broonie@kernel.org> Link: https://lore.kernel.org/r/1587844788-33997-1-git-send-email-sanju.mehta@amd.com Signed-off-by: Mark Brown <broonie@kernel.org>
2020-04-25 14:59:48 -05:00
spi: spi_amd: Optimize IO operations Read and write the maximum number of data bytes at once, rather than byte by byte. This improves AMD SPI controller driver performance by reducing the time required to access FIFO registers. For example, with the new changes, 64 bytes of data from the FIFO queue can be read in 8 read calls (8 bytes per call) instead of 64 read calls(1 byte per call). Co-developed-by: Krishnamoorthi M <krishnamoorthi.m@amd.com> Signed-off-by: Krishnamoorthi M <krishnamoorthi.m@amd.com> Co-developed-by: Akshata MukundShetty <akshata.mukundshetty@amd.com> Signed-off-by: Akshata MukundShetty <akshata.mukundshetty@amd.com> Signed-off-by: Raju Rangoju <Raju.Rangoju@amd.com> Link: https://patch.msgid.link/20240925133644.2922359-6-Raju.Rangoju@amd.com Signed-off-by: Mark Brown <broonie@kernel.org>
2024-09-25 19:06:41 +05:30
spi: amd: Refactor code to use less spi_master_get_devdata Get master data in the start and then just use struct amd_spi as it has the needed variable Signed-off-by: Lucas Tanure <tanureal@opensource.cirrus.com> Reviewed-by: Charles Keepax <ckeepax@opensource.cirrus.com> Link: https://lore.kernel.org/r/20210910111529.12539-1-tanureal@opensource.cirrus.com Signed-off-by: Mark Brown <broonie@kernel.org>
2021-09-10 12:15:26 +01:00
spi: spi-amd: Add AMD SPI controller driver support This driver supports SPI Controller for AMD SOCs.This driver supports SPI operations using FIFO mode of transfer. Signed-off-by: Sanjay R Mehta <sanju.mehta@amd.com> Signed-off-by: Mark Brown <broonie@kernel.org> Link: https://lore.kernel.org/r/1587844788-33997-1-git-send-email-sanju.mehta@amd.com Signed-off-by: Mark Brown <broonie@kernel.org>
2020-04-25 14:59:48 -05:00
spi: amd: Refactor code to use less spi_master_get_devdata Get master data in the start and then just use struct amd_spi as it has the needed variable Signed-off-by: Lucas Tanure <tanureal@opensource.cirrus.com> Reviewed-by: Charles Keepax <ckeepax@opensource.cirrus.com> Link: https://lore.kernel.org/r/20210910111529.12539-1-tanureal@opensource.cirrus.com Signed-off-by: Mark Brown <broonie@kernel.org>
2021-09-10 12:15:26 +01:00
spi: spi-amd: Add AMD SPI controller driver support This driver supports SPI Controller for AMD SOCs.This driver supports SPI operations using FIFO mode of transfer. Signed-off-by: Sanjay R Mehta <sanju.mehta@amd.com> Signed-off-by: Mark Brown <broonie@kernel.org> Link: https://lore.kernel.org/r/1587844788-33997-1-git-send-email-sanju.mehta@amd.com Signed-off-by: Mark Brown <broonie@kernel.org>
2020-04-25 14:59:48 -05:00
spi: amd: Refactor code to use less spi_master_get_devdata Get master data in the start and then just use struct amd_spi as it has the needed variable Signed-off-by: Lucas Tanure <tanureal@opensource.cirrus.com> Reviewed-by: Charles Keepax <ckeepax@opensource.cirrus.com> Link: https://lore.kernel.org/r/20210910111529.12539-1-tanureal@opensource.cirrus.com Signed-off-by: Mark Brown <broonie@kernel.org>
2021-09-10 12:15:26 +01:00
spi: spi-amd: Add AMD SPI controller driver support This driver supports SPI Controller for AMD SOCs.This driver supports SPI operations using FIFO mode of transfer. Signed-off-by: Sanjay R Mehta <sanju.mehta@amd.com> Signed-off-by: Mark Brown <broonie@kernel.org> Link: https://lore.kernel.org/r/1587844788-33997-1-git-send-email-sanju.mehta@amd.com Signed-off-by: Mark Brown <broonie@kernel.org>
2020-04-25 14:59:48 -05:00
spi: amd: Remove unneeded variable Remove internal cs from amd_spi Signed-off-by: Lucas Tanure <tanureal@opensource.cirrus.com> Reviewed-by: Charles Keepax <ckeepax@opensource.cirrus.com> Link: https://lore.kernel.org/r/20210910111529.12539-3-tanureal@opensource.cirrus.com Signed-off-by: Mark Brown <broonie@kernel.org>
2021-09-10 12:15:28 +01:00
spi: spi-amd: Add AMD SPI controller driver support This driver supports SPI Controller for AMD SOCs.This driver supports SPI operations using FIFO mode of transfer. Signed-off-by: Sanjay R Mehta <sanju.mehta@amd.com> Signed-off-by: Mark Brown <broonie@kernel.org> Link: https://lore.kernel.org/r/1587844788-33997-1-git-send-email-sanju.mehta@amd.com Signed-off-by: Mark Brown <broonie@kernel.org>
2020-04-25 14:59:48 -05:00
spi: amd: Remove unneeded variable Remove internal cs from amd_spi Signed-off-by: Lucas Tanure <tanureal@opensource.cirrus.com> Reviewed-by: Charles Keepax <ckeepax@opensource.cirrus.com> Link: https://lore.kernel.org/r/20210910111529.12539-3-tanureal@opensource.cirrus.com Signed-off-by: Mark Brown <broonie@kernel.org>
2021-09-10 12:15:28 +01:00
spi: spi-amd: Add AMD SPI controller driver support This driver supports SPI Controller for AMD SOCs.This driver supports SPI operations using FIFO mode of transfer. Signed-off-by: Sanjay R Mehta <sanju.mehta@amd.com> Signed-off-by: Mark Brown <broonie@kernel.org> Link: https://lore.kernel.org/r/1587844788-33997-1-git-send-email-sanju.mehta@amd.com Signed-off-by: Mark Brown <broonie@kernel.org>
2020-04-25 14:59:48 -05:00
spi: amd: Add support for version AMDI0062 Add support for the AMD SPI controller version AMDI0062. Do this in a modular way where's easy to add new versions. Signed-off-by: André Almeida <andrealmeid@collabora.com> Link: https://lore.kernel.org/r/20220211143155.75513-4-andrealmeid@collabora.com Signed-off-by: Mark Brown <broonie@kernel.org>
2022-02-11 11:31:55 -03:00
spi: amd: Refactor code to use less spi_master_get_devdata Get master data in the start and then just use struct amd_spi as it has the needed variable Signed-off-by: Lucas Tanure <tanureal@opensource.cirrus.com> Reviewed-by: Charles Keepax <ckeepax@opensource.cirrus.com> Link: https://lore.kernel.org/r/20210910111529.12539-1-tanureal@opensource.cirrus.com Signed-off-by: Mark Brown <broonie@kernel.org>
2021-09-10 12:15:26 +01:00
spi: spi-amd: Add AMD SPI controller driver support This driver supports SPI Controller for AMD SOCs.This driver supports SPI operations using FIFO mode of transfer. Signed-off-by: Sanjay R Mehta <sanju.mehta@amd.com> Signed-off-by: Mark Brown <broonie@kernel.org> Link: https://lore.kernel.org/r/1587844788-33997-1-git-send-email-sanju.mehta@amd.com Signed-off-by: Mark Brown <broonie@kernel.org>
2020-04-25 14:59:48 -05:00
spi: amd: Refactor code to use less spi_master_get_devdata Get master data in the start and then just use struct amd_spi as it has the needed variable Signed-off-by: Lucas Tanure <tanureal@opensource.cirrus.com> Reviewed-by: Charles Keepax <ckeepax@opensource.cirrus.com> Link: https://lore.kernel.org/r/20210910111529.12539-1-tanureal@opensource.cirrus.com Signed-off-by: Mark Brown <broonie@kernel.org>
2021-09-10 12:15:26 +01:00
spi: spi-amd: Add AMD SPI controller driver support This driver supports SPI Controller for AMD SOCs.This driver supports SPI operations using FIFO mode of transfer. Signed-off-by: Sanjay R Mehta <sanju.mehta@amd.com> Signed-off-by: Mark Brown <broonie@kernel.org> Link: https://lore.kernel.org/r/1587844788-33997-1-git-send-email-sanju.mehta@amd.com Signed-off-by: Mark Brown <broonie@kernel.org>
2020-04-25 14:59:48 -05:00
spi: amd: Add support for version AMDI0062 Add support for the AMD SPI controller version AMDI0062. Do this in a modular way where's easy to add new versions. Signed-off-by: André Almeida <andrealmeid@collabora.com> Link: https://lore.kernel.org/r/20220211143155.75513-4-andrealmeid@collabora.com Signed-off-by: Mark Brown <broonie@kernel.org>
2022-02-11 11:31:55 -03:00
spi: spi-amd: Add AMD SPI controller driver support This driver supports SPI Controller for AMD SOCs.This driver supports SPI operations using FIFO mode of transfer. Signed-off-by: Sanjay R Mehta <sanju.mehta@amd.com> Signed-off-by: Mark Brown <broonie@kernel.org> Link: https://lore.kernel.org/r/1587844788-33997-1-git-send-email-sanju.mehta@amd.com Signed-off-by: Mark Brown <broonie@kernel.org>
2020-04-25 14:59:48 -05:00
spi: amd: Add support for version AMDI0062 Add support for the AMD SPI controller version AMDI0062. Do this in a modular way where's easy to add new versions. Signed-off-by: André Almeida <andrealmeid@collabora.com> Link: https://lore.kernel.org/r/20220211143155.75513-4-andrealmeid@collabora.com Signed-off-by: Mark Brown <broonie@kernel.org>
2022-02-11 11:31:55 -03:00
spi: spi_amd: Add support for HID2 SPI controller AMD SoC has HID2 SPI controller in addition to the existing SPI0 controller(AMDI0062). Add HID2 SPI controller's ACPI ID AMDI0063 with its version ID to the list of supported devices. Use the version ID to differentiate the register offsets. And, the AMD HID2 SPI controller supports DMA read, allowing for up to 4 KB of data to be read in single transaction. Update the SPI-MEM support function to reflect this capability. Co-developed-by: Krishnamoorthi M <krishnamoorthi.m@amd.com> Signed-off-by: Krishnamoorthi M <krishnamoorthi.m@amd.com> Co-developed-by: Akshata MukundShetty <akshata.mukundshetty@amd.com> Signed-off-by: Akshata MukundShetty <akshata.mukundshetty@amd.com> Signed-off-by: Raju Rangoju <Raju.Rangoju@amd.com> Link: https://patch.msgid.link/20240925133644.2922359-7-Raju.Rangoju@amd.com Signed-off-by: Mark Brown <broonie@kernel.org>
2024-09-25 19:06:42 +05:30
spi: amd: Add support for version AMDI0062 Add support for the AMD SPI controller version AMDI0062. Do this in a modular way where's easy to add new versions. Signed-off-by: André Almeida <andrealmeid@collabora.com> Link: https://lore.kernel.org/r/20220211143155.75513-4-andrealmeid@collabora.com Signed-off-by: Mark Brown <broonie@kernel.org>
2022-02-11 11:31:55 -03:00
spi: spi-amd: Add AMD SPI controller driver support This driver supports SPI Controller for AMD SOCs.This driver supports SPI operations using FIFO mode of transfer. Signed-off-by: Sanjay R Mehta <sanju.mehta@amd.com> Signed-off-by: Mark Brown <broonie@kernel.org> Link: https://lore.kernel.org/r/1587844788-33997-1-git-send-email-sanju.mehta@amd.com Signed-off-by: Mark Brown <broonie@kernel.org>
2020-04-25 14:59:48 -05:00
spi: amd: Refactor code to use less spi_master_get_devdata Get master data in the start and then just use struct amd_spi as it has the needed variable Signed-off-by: Lucas Tanure <tanureal@opensource.cirrus.com> Reviewed-by: Charles Keepax <ckeepax@opensource.cirrus.com> Link: https://lore.kernel.org/r/20210910111529.12539-1-tanureal@opensource.cirrus.com Signed-off-by: Mark Brown <broonie@kernel.org>
2021-09-10 12:15:26 +01:00
spi: spi-amd: Add AMD SPI controller driver support This driver supports SPI Controller for AMD SOCs.This driver supports SPI operations using FIFO mode of transfer. Signed-off-by: Sanjay R Mehta <sanju.mehta@amd.com> Signed-off-by: Mark Brown <broonie@kernel.org> Link: https://lore.kernel.org/r/1587844788-33997-1-git-send-email-sanju.mehta@amd.com Signed-off-by: Mark Brown <broonie@kernel.org>
2020-04-25 14:59:48 -05:00
spi: spi_amd: Updates to set tx/rx count functions AMD SPI TX and RX counter registers are 1-byte length registers. The existing value will be overwritten during register write, so masking is not required. Co-developed-by: Krishnamoorthi M <krishnamoorthi.m@amd.com> Signed-off-by: Krishnamoorthi M <krishnamoorthi.m@amd.com> Co-developed-by: Akshata MukundShetty <akshata.mukundshetty@amd.com> Signed-off-by: Akshata MukundShetty <akshata.mukundshetty@amd.com> Signed-off-by: Raju Rangoju <Raju.Rangoju@amd.com> Link: https://patch.msgid.link/20240925133644.2922359-5-Raju.Rangoju@amd.com Signed-off-by: Mark Brown <broonie@kernel.org>
2024-09-25 19:06:40 +05:30
spi: spi-amd: Add AMD SPI controller driver support This driver supports SPI Controller for AMD SOCs.This driver supports SPI operations using FIFO mode of transfer. Signed-off-by: Sanjay R Mehta <sanju.mehta@amd.com> Signed-off-by: Mark Brown <broonie@kernel.org> Link: https://lore.kernel.org/r/1587844788-33997-1-git-send-email-sanju.mehta@amd.com Signed-off-by: Mark Brown <broonie@kernel.org>
2020-04-25 14:59:48 -05:00
spi: amd: Refactor code to use less spi_master_get_devdata Get master data in the start and then just use struct amd_spi as it has the needed variable Signed-off-by: Lucas Tanure <tanureal@opensource.cirrus.com> Reviewed-by: Charles Keepax <ckeepax@opensource.cirrus.com> Link: https://lore.kernel.org/r/20210910111529.12539-1-tanureal@opensource.cirrus.com Signed-off-by: Mark Brown <broonie@kernel.org>
2021-09-10 12:15:26 +01:00
spi: spi-amd: Add AMD SPI controller driver support This driver supports SPI Controller for AMD SOCs.This driver supports SPI operations using FIFO mode of transfer. Signed-off-by: Sanjay R Mehta <sanju.mehta@amd.com> Signed-off-by: Mark Brown <broonie@kernel.org> Link: https://lore.kernel.org/r/1587844788-33997-1-git-send-email-sanju.mehta@amd.com Signed-off-by: Mark Brown <broonie@kernel.org>
2020-04-25 14:59:48 -05:00
spi: spi_amd: Updates to set tx/rx count functions AMD SPI TX and RX counter registers are 1-byte length registers. The existing value will be overwritten during register write, so masking is not required. Co-developed-by: Krishnamoorthi M <krishnamoorthi.m@amd.com> Signed-off-by: Krishnamoorthi M <krishnamoorthi.m@amd.com> Co-developed-by: Akshata MukundShetty <akshata.mukundshetty@amd.com> Signed-off-by: Akshata MukundShetty <akshata.mukundshetty@amd.com> Signed-off-by: Raju Rangoju <Raju.Rangoju@amd.com> Link: https://patch.msgid.link/20240925133644.2922359-5-Raju.Rangoju@amd.com Signed-off-by: Mark Brown <broonie@kernel.org>
2024-09-25 19:06:40 +05:30
spi: spi-amd: Add AMD SPI controller driver support This driver supports SPI Controller for AMD SOCs.This driver supports SPI operations using FIFO mode of transfer. Signed-off-by: Sanjay R Mehta <sanju.mehta@amd.com> Signed-off-by: Mark Brown <broonie@kernel.org> Link: https://lore.kernel.org/r/1587844788-33997-1-git-send-email-sanju.mehta@amd.com Signed-off-by: Mark Brown <broonie@kernel.org>
2020-04-25 14:59:48 -05:00
spi: amd: Refactor amd_spi_busy_wait Use amd_spi_readreg32 to read 32 bits registers Signed-off-by: Lucas Tanure <tanureal@opensource.cirrus.com> Reviewed-by: Charles Keepax <ckeepax@opensource.cirrus.com> Link: https://lore.kernel.org/r/20210910111529.12539-2-tanureal@opensource.cirrus.com Signed-off-by: Mark Brown <broonie@kernel.org>
2021-09-10 12:15:27 +01:00
spi: spi-amd: Add AMD SPI controller driver support This driver supports SPI Controller for AMD SOCs.This driver supports SPI operations using FIFO mode of transfer. Signed-off-by: Sanjay R Mehta <sanju.mehta@amd.com> Signed-off-by: Mark Brown <broonie@kernel.org> Link: https://lore.kernel.org/r/1587844788-33997-1-git-send-email-sanju.mehta@amd.com Signed-off-by: Mark Brown <broonie@kernel.org>
2020-04-25 14:59:48 -05:00
spi: amd: Use iopoll for busy waiting Instead of implementing a custom IO busy wait function, just use readl_poll_timeout(). Signed-off-by: André Almeida <andrealmeid@collabora.com> Link: https://lore.kernel.org/r/20220211143155.75513-2-andrealmeid@collabora.com Signed-off-by: Mark Brown <broonie@kernel.org>
2022-02-11 11:31:53 -03:00
spi: amd: Add support for version AMDI0062 Add support for the AMD SPI controller version AMDI0062. Do this in a modular way where's easy to add new versions. Signed-off-by: André Almeida <andrealmeid@collabora.com> Link: https://lore.kernel.org/r/20220211143155.75513-4-andrealmeid@collabora.com Signed-off-by: Mark Brown <broonie@kernel.org>
2022-02-11 11:31:55 -03:00
spi: spi-amd: Add AMD SPI controller driver support This driver supports SPI Controller for AMD SOCs.This driver supports SPI operations using FIFO mode of transfer. Signed-off-by: Sanjay R Mehta <sanju.mehta@amd.com> Signed-off-by: Mark Brown <broonie@kernel.org> Link: https://lore.kernel.org/r/1587844788-33997-1-git-send-email-sanju.mehta@amd.com Signed-off-by: Mark Brown <broonie@kernel.org>
2020-04-25 14:59:48 -05:00
spi: amd: Add support for version AMDI0062 Add support for the AMD SPI controller version AMDI0062. Do this in a modular way where's easy to add new versions. Signed-off-by: André Almeida <andrealmeid@collabora.com> Link: https://lore.kernel.org/r/20220211143155.75513-4-andrealmeid@collabora.com Signed-off-by: Mark Brown <broonie@kernel.org>
2022-02-11 11:31:55 -03:00
spi: spi_amd: Add support for HID2 SPI controller AMD SoC has HID2 SPI controller in addition to the existing SPI0 controller(AMDI0062). Add HID2 SPI controller's ACPI ID AMDI0063 with its version ID to the list of supported devices. Use the version ID to differentiate the register offsets. And, the AMD HID2 SPI controller supports DMA read, allowing for up to 4 KB of data to be read in single transaction. Update the SPI-MEM support function to reflect this capability. Co-developed-by: Krishnamoorthi M <krishnamoorthi.m@amd.com> Signed-off-by: Krishnamoorthi M <krishnamoorthi.m@amd.com> Co-developed-by: Akshata MukundShetty <akshata.mukundshetty@amd.com> Signed-off-by: Akshata MukundShetty <akshata.mukundshetty@amd.com> Signed-off-by: Raju Rangoju <Raju.Rangoju@amd.com> Link: https://patch.msgid.link/20240925133644.2922359-7-Raju.Rangoju@amd.com Signed-off-by: Mark Brown <broonie@kernel.org>
2024-09-25 19:06:42 +05:30
spi: amd: Add support for version AMDI0062 Add support for the AMD SPI controller version AMDI0062. Do this in a modular way where's easy to add new versions. Signed-off-by: André Almeida <andrealmeid@collabora.com> Link: https://lore.kernel.org/r/20220211143155.75513-4-andrealmeid@collabora.com Signed-off-by: Mark Brown <broonie@kernel.org>
2022-02-11 11:31:55 -03:00
spi: spi-amd: Add AMD SPI controller driver support This driver supports SPI Controller for AMD SOCs.This driver supports SPI operations using FIFO mode of transfer. Signed-off-by: Sanjay R Mehta <sanju.mehta@amd.com> Signed-off-by: Mark Brown <broonie@kernel.org> Link: https://lore.kernel.org/r/1587844788-33997-1-git-send-email-sanju.mehta@amd.com Signed-off-by: Mark Brown <broonie@kernel.org>
2020-04-25 14:59:48 -05:00
spi: amd: Don't wait for a write-only transfer to finish Return from a write-only transfer without waiting for it to finish But wait before a new transfer as the previous may still happening and also wait before reading the data from the FIFO Signed-off-by: Lucas Tanure <tanureal@opensource.cirrus.com> Reviewed-by: Charles Keepax <ckeepax@opensource.cirrus.com> Link: https://lore.kernel.org/r/20210910111529.12539-4-tanureal@opensource.cirrus.com Signed-off-by: Mark Brown <broonie@kernel.org>
2021-09-10 12:15:29 +01:00
spi: spi-amd: Add AMD SPI controller driver support This driver supports SPI Controller for AMD SOCs.This driver supports SPI operations using FIFO mode of transfer. Signed-off-by: Sanjay R Mehta <sanju.mehta@amd.com> Signed-off-by: Mark Brown <broonie@kernel.org> Link: https://lore.kernel.org/r/1587844788-33997-1-git-send-email-sanju.mehta@amd.com Signed-off-by: Mark Brown <broonie@kernel.org>
2020-04-25 14:59:48 -05:00
spi: amd: Don't wait for a write-only transfer to finish Return from a write-only transfer without waiting for it to finish But wait before a new transfer as the previous may still happening and also wait before reading the data from the FIFO Signed-off-by: Lucas Tanure <tanureal@opensource.cirrus.com> Reviewed-by: Charles Keepax <ckeepax@opensource.cirrus.com> Link: https://lore.kernel.org/r/20210910111529.12539-4-tanureal@opensource.cirrus.com Signed-off-by: Mark Brown <broonie@kernel.org>
2021-09-10 12:15:29 +01:00
spi: amd: Add support for version AMDI0062 Add support for the AMD SPI controller version AMDI0062. Do this in a modular way where's easy to add new versions. Signed-off-by: André Almeida <andrealmeid@collabora.com> Link: https://lore.kernel.org/r/20220211143155.75513-4-andrealmeid@collabora.com Signed-off-by: Mark Brown <broonie@kernel.org>
2022-02-11 11:31:55 -03:00
spi: spi_amd: Add support for HID2 SPI controller AMD SoC has HID2 SPI controller in addition to the existing SPI0 controller(AMDI0062). Add HID2 SPI controller's ACPI ID AMDI0063 with its version ID to the list of supported devices. Use the version ID to differentiate the register offsets. And, the AMD HID2 SPI controller supports DMA read, allowing for up to 4 KB of data to be read in single transaction. Update the SPI-MEM support function to reflect this capability. Co-developed-by: Krishnamoorthi M <krishnamoorthi.m@amd.com> Signed-off-by: Krishnamoorthi M <krishnamoorthi.m@amd.com> Co-developed-by: Akshata MukundShetty <akshata.mukundshetty@amd.com> Signed-off-by: Akshata MukundShetty <akshata.mukundshetty@amd.com> Signed-off-by: Raju Rangoju <Raju.Rangoju@amd.com> Link: https://patch.msgid.link/20240925133644.2922359-7-Raju.Rangoju@amd.com Signed-off-by: Mark Brown <broonie@kernel.org>
2024-09-25 19:06:42 +05:30
spi: amd: Add support for version AMDI0062 Add support for the AMD SPI controller version AMDI0062. Do this in a modular way where's easy to add new versions. Signed-off-by: André Almeida <andrealmeid@collabora.com> Link: https://lore.kernel.org/r/20220211143155.75513-4-andrealmeid@collabora.com Signed-off-by: Mark Brown <broonie@kernel.org>
2022-02-11 11:31:55 -03:00
spi: spi-amd: Add AMD SPI controller driver support This driver supports SPI Controller for AMD SOCs.This driver supports SPI operations using FIFO mode of transfer. Signed-off-by: Sanjay R Mehta <sanju.mehta@amd.com> Signed-off-by: Mark Brown <broonie@kernel.org> Link: https://lore.kernel.org/r/1587844788-33997-1-git-send-email-sanju.mehta@amd.com Signed-off-by: Mark Brown <broonie@kernel.org>
2020-04-25 14:59:48 -05:00
spi: amd: switch to use modern name Change legacy name master to modern name host or controller. No functional changed. Signed-off-by: Yang Yingliang <yangyingliang@huawei.com> Link: https://lore.kernel.org/r/20230728093221.3312026-2-yangyingliang@huawei.com Signed-off-by: Mark Brown <broonie@kernel.org>
2023-07-28 17:32:01 +08:00
spi: spi-amd: Add AMD SPI controller driver support This driver supports SPI Controller for AMD SOCs.This driver supports SPI operations using FIFO mode of transfer. Signed-off-by: Sanjay R Mehta <sanju.mehta@amd.com> Signed-off-by: Mark Brown <broonie@kernel.org> Link: https://lore.kernel.org/r/1587844788-33997-1-git-send-email-sanju.mehta@amd.com Signed-off-by: Mark Brown <broonie@kernel.org>
2020-04-25 14:59:48 -05:00
spi: amd: switch to use modern name Change legacy name master to modern name host or controller. No functional changed. Signed-off-by: Yang Yingliang <yangyingliang@huawei.com> Link: https://lore.kernel.org/r/20230728093221.3312026-2-yangyingliang@huawei.com Signed-off-by: Mark Brown <broonie@kernel.org>
2023-07-28 17:32:01 +08:00
spi: spi-amd: Add AMD SPI controller driver support This driver supports SPI Controller for AMD SOCs.This driver supports SPI operations using FIFO mode of transfer. Signed-off-by: Sanjay R Mehta <sanju.mehta@amd.com> Signed-off-by: Mark Brown <broonie@kernel.org> Link: https://lore.kernel.org/r/1587844788-33997-1-git-send-email-sanju.mehta@amd.com Signed-off-by: Mark Brown <broonie@kernel.org>
2020-04-25 14:59:48 -05:00
spi: amd: Refactor code to use less spi_master_get_devdata Get master data in the start and then just use struct amd_spi as it has the needed variable Signed-off-by: Lucas Tanure <tanureal@opensource.cirrus.com> Reviewed-by: Charles Keepax <ckeepax@opensource.cirrus.com> Link: https://lore.kernel.org/r/20210910111529.12539-1-tanureal@opensource.cirrus.com Signed-off-by: Mark Brown <broonie@kernel.org>
2021-09-10 12:15:26 +01:00
spi: spi-amd: Add AMD SPI controller driver support This driver supports SPI Controller for AMD SOCs.This driver supports SPI operations using FIFO mode of transfer. Signed-off-by: Sanjay R Mehta <sanju.mehta@amd.com> Signed-off-by: Mark Brown <broonie@kernel.org> Link: https://lore.kernel.org/r/1587844788-33997-1-git-send-email-sanju.mehta@amd.com Signed-off-by: Mark Brown <broonie@kernel.org>
2020-04-25 14:59:48 -05:00
spi: amd: Configure device speed Number of clock frequencies are supported by AMD controller which are mentioned in the amd_spi_freq structure table. Create mechanism to configure device clock frequency such that it is strictly less than the requested frequency. Give priority to the device transfer speed and in case it is not set then use the max clock speed supported by the device. Signed-off-by: Lucas Tanure <tanureal@opensource.cirrus.com> Co-developed-by: Shreeya Patel <shreeya.patel@collabora.com> Signed-off-by: Shreeya Patel <shreeya.patel@collabora.com> Link: https://lore.kernel.org/r/20220825143132.253224-1-shreeya.patel@collabora.com Signed-off-by: Mark Brown <broonie@kernel.org>
2022-08-25 20:01:32 +05:30
spi: amd: Drop redundant check Both spi and spi-mem cores already take care of checking the minimum and maximum speed for transfers depending on the controller capabilities. There is no reason to repeat this check in controller drivers. Once this possible error condition removed from the function, it makes no longer sense to return an int. Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> Link: https://patch.msgid.link/20241224-winbond-6-11-rc1-quad-support-v2-4-ad218dbc406f@bootlin.com Signed-off-by: Mark Brown <broonie@kernel.org>
2024-12-24 18:05:49 +01:00
spi: amd: Configure device speed Number of clock frequencies are supported by AMD controller which are mentioned in the amd_spi_freq structure table. Create mechanism to configure device clock frequency such that it is strictly less than the requested frequency. Give priority to the device transfer speed and in case it is not set then use the max clock speed supported by the device. Signed-off-by: Lucas Tanure <tanureal@opensource.cirrus.com> Co-developed-by: Shreeya Patel <shreeya.patel@collabora.com> Signed-off-by: Shreeya Patel <shreeya.patel@collabora.com> Link: https://lore.kernel.org/r/20220825143132.253224-1-shreeya.patel@collabora.com Signed-off-by: Mark Brown <broonie@kernel.org>
2022-08-25 20:01:32 +05:30
objtool, spi: amd: Fix out-of-bounds stack access in amd_set_spi_freq() If speed_hz < AMD_SPI_MIN_HZ, amd_set_spi_freq() iterates over the entire amd_spi_freq array without breaking out early, causing 'i' to go beyond the array bounds. Fix that by stopping the loop when it gets to the last entry, so the low speed_hz value gets clamped up to AMD_SPI_MIN_HZ. Fixes the following warning with an UBSAN kernel: drivers/spi/spi-amd.o: error: objtool: amd_set_spi_freq() falls through to next function amd_spi_set_opcode() Fixes: 3fe26121dc3a ("spi: amd: Configure device speed") Reported-by: kernel test robot <lkp@intel.com> Signed-off-by: Josh Poimboeuf <jpoimboe@kernel.org> Signed-off-by: Ingo Molnar <mingo@kernel.org> Acked-by: Mark Brown <broonie@kernel.org> Cc: Raju Rangoju <Raju.Rangoju@amd.com> Cc: Linus Torvalds <torvalds@linux-foundation.org> Link: https://lore.kernel.org/r/78fef0f2434f35be9095bcc9ffa23dd8cab667b9.1742852847.git.jpoimboe@kernel.org Closes: https://lore.kernel.org/r/202503161828.RUk9EhWx-lkp@intel.com/
2025-03-24 14:56:04 -07:00
spi: amd: Configure device speed Number of clock frequencies are supported by AMD controller which are mentioned in the amd_spi_freq structure table. Create mechanism to configure device clock frequency such that it is strictly less than the requested frequency. Give priority to the device transfer speed and in case it is not set then use the max clock speed supported by the device. Signed-off-by: Lucas Tanure <tanureal@opensource.cirrus.com> Co-developed-by: Shreeya Patel <shreeya.patel@collabora.com> Signed-off-by: Shreeya Patel <shreeya.patel@collabora.com> Link: https://lore.kernel.org/r/20220825143132.253224-1-shreeya.patel@collabora.com Signed-off-by: Mark Brown <broonie@kernel.org>
2022-08-25 20:01:32 +05:30
spi: amd: Fix speed selection If the current speed is equal to the requested speed by the device then return success. This patch fixes a bug introduced by the commit 3fe26121dc3a ("spi: amd: Configure device speed") which checks speed_hz instead of amd_spi->speed_hz. Fixes: 3fe26121dc3a ("spi: amd: Configure device speed") Signed-off-by: Shreeya Patel <shreeya.patel@collabora.com> Link: https://lore.kernel.org/r/20220830093607.45484-1-shreeya.patel@collabora.com Signed-off-by: Mark Brown <broonie@kernel.org>
2022-08-30 15:06:07 +05:30
spi: amd: Drop redundant check Both spi and spi-mem cores already take care of checking the minimum and maximum speed for transfers depending on the controller capabilities. There is no reason to repeat this check in controller drivers. Once this possible error condition removed from the function, it makes no longer sense to return an int. Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> Link: https://patch.msgid.link/20241224-winbond-6-11-rc1-quad-support-v2-4-ad218dbc406f@bootlin.com Signed-off-by: Mark Brown <broonie@kernel.org>
2024-12-24 18:05:49 +01:00
spi: amd: Configure device speed Number of clock frequencies are supported by AMD controller which are mentioned in the amd_spi_freq structure table. Create mechanism to configure device clock frequency such that it is strictly less than the requested frequency. Give priority to the device transfer speed and in case it is not set then use the max clock speed supported by the device. Signed-off-by: Lucas Tanure <tanureal@opensource.cirrus.com> Co-developed-by: Shreeya Patel <shreeya.patel@collabora.com> Signed-off-by: Shreeya Patel <shreeya.patel@collabora.com> Link: https://lore.kernel.org/r/20220825143132.253224-1-shreeya.patel@collabora.com Signed-off-by: Mark Brown <broonie@kernel.org>
2022-08-25 20:01:32 +05:30
spi: spi-amd: Add AMD SPI controller driver support This driver supports SPI Controller for AMD SOCs.This driver supports SPI operations using FIFO mode of transfer. Signed-off-by: Sanjay R Mehta <sanju.mehta@amd.com> Signed-off-by: Mark Brown <broonie@kernel.org> Link: https://lore.kernel.org/r/1587844788-33997-1-git-send-email-sanju.mehta@amd.com Signed-off-by: Mark Brown <broonie@kernel.org>
2020-04-25 14:59:48 -05:00
spi: amd: switch to use modern name Change legacy name master to modern name host or controller. No functional changed. Signed-off-by: Yang Yingliang <yangyingliang@huawei.com> Link: https://lore.kernel.org/r/20230728093221.3312026-2-yangyingliang@huawei.com Signed-off-by: Mark Brown <broonie@kernel.org>
2023-07-28 17:32:01 +08:00
spi: spi-amd: Add AMD SPI controller driver support This driver supports SPI Controller for AMD SOCs.This driver supports SPI operations using FIFO mode of transfer. Signed-off-by: Sanjay R Mehta <sanju.mehta@amd.com> Signed-off-by: Mark Brown <broonie@kernel.org> Link: https://lore.kernel.org/r/1587844788-33997-1-git-send-email-sanju.mehta@amd.com Signed-off-by: Mark Brown <broonie@kernel.org>
2020-04-25 14:59:48 -05:00
spi: amd: Configure device speed Number of clock frequencies are supported by AMD controller which are mentioned in the amd_spi_freq structure table. Create mechanism to configure device clock frequency such that it is strictly less than the requested frequency. Give priority to the device transfer speed and in case it is not set then use the max clock speed supported by the device. Signed-off-by: Lucas Tanure <tanureal@opensource.cirrus.com> Co-developed-by: Shreeya Patel <shreeya.patel@collabora.com> Signed-off-by: Shreeya Patel <shreeya.patel@collabora.com> Link: https://lore.kernel.org/r/20220825143132.253224-1-shreeya.patel@collabora.com Signed-off-by: Mark Brown <broonie@kernel.org>
2022-08-25 20:01:32 +05:30
spi: amd: Setup all xfers before opcode execution The AMD SPI controller hardware seems to expect the FIFO buffer to be fully setup with the details of all transfers in the SPI message before it is able to start processing the data in a reliable way. Furthermore, it imposes a strict ordering restriction, in the sense that all TX transfers must be handled prior any RX transfer. Hence, let's ensure amd_spi_execute_opcode() is called only once, after all TX transfers have been setup, and process any remaining RX transfers afterwards, in a second iteration. Additionally, get rid of the unnecessary AMD_SPI_XFER_TX/RX defines and improve error handling. Signed-off-by: Cristian Ciocaltea <cristian.ciocaltea@collabora.com> Link: https://lore.kernel.org/r/20220818010059.403776-1-cristian.ciocaltea@collabora.com Signed-off-by: Mark Brown <broonie@kernel.org>
2022-08-18 04:00:59 +03:00
spi: spi-amd: Add AMD SPI controller driver support This driver supports SPI Controller for AMD SOCs.This driver supports SPI operations using FIFO mode of transfer. Signed-off-by: Sanjay R Mehta <sanju.mehta@amd.com> Signed-off-by: Mark Brown <broonie@kernel.org> Link: https://lore.kernel.org/r/1587844788-33997-1-git-send-email-sanju.mehta@amd.com Signed-off-by: Mark Brown <broonie@kernel.org>
2020-04-25 14:59:48 -05:00
spi: amd: Configure device speed Number of clock frequencies are supported by AMD controller which are mentioned in the amd_spi_freq structure table. Create mechanism to configure device clock frequency such that it is strictly less than the requested frequency. Give priority to the device transfer speed and in case it is not set then use the max clock speed supported by the device. Signed-off-by: Lucas Tanure <tanureal@opensource.cirrus.com> Co-developed-by: Shreeya Patel <shreeya.patel@collabora.com> Signed-off-by: Shreeya Patel <shreeya.patel@collabora.com> Link: https://lore.kernel.org/r/20220825143132.253224-1-shreeya.patel@collabora.com Signed-off-by: Mark Brown <broonie@kernel.org>
2022-08-25 20:01:32 +05:30
spi: amd: Setup all xfers before opcode execution The AMD SPI controller hardware seems to expect the FIFO buffer to be fully setup with the details of all transfers in the SPI message before it is able to start processing the data in a reliable way. Furthermore, it imposes a strict ordering restriction, in the sense that all TX transfers must be handled prior any RX transfer. Hence, let's ensure amd_spi_execute_opcode() is called only once, after all TX transfers have been setup, and process any remaining RX transfers afterwards, in a second iteration. Additionally, get rid of the unnecessary AMD_SPI_XFER_TX/RX defines and improve error handling. Signed-off-by: Cristian Ciocaltea <cristian.ciocaltea@collabora.com> Link: https://lore.kernel.org/r/20220818010059.403776-1-cristian.ciocaltea@collabora.com Signed-off-by: Mark Brown <broonie@kernel.org>
2022-08-18 04:00:59 +03:00
spi: spi-amd: Add AMD SPI controller driver support This driver supports SPI Controller for AMD SOCs.This driver supports SPI operations using FIFO mode of transfer. Signed-off-by: Sanjay R Mehta <sanju.mehta@amd.com> Signed-off-by: Mark Brown <broonie@kernel.org> Link: https://lore.kernel.org/r/1587844788-33997-1-git-send-email-sanju.mehta@amd.com Signed-off-by: Mark Brown <broonie@kernel.org>
2020-04-25 14:59:48 -05:00
spi: amd: Setup all xfers before opcode execution The AMD SPI controller hardware seems to expect the FIFO buffer to be fully setup with the details of all transfers in the SPI message before it is able to start processing the data in a reliable way. Furthermore, it imposes a strict ordering restriction, in the sense that all TX transfers must be handled prior any RX transfer. Hence, let's ensure amd_spi_execute_opcode() is called only once, after all TX transfers have been setup, and process any remaining RX transfers afterwards, in a second iteration. Additionally, get rid of the unnecessary AMD_SPI_XFER_TX/RX defines and improve error handling. Signed-off-by: Cristian Ciocaltea <cristian.ciocaltea@collabora.com> Link: https://lore.kernel.org/r/20220818010059.403776-1-cristian.ciocaltea@collabora.com Signed-off-by: Mark Brown <broonie@kernel.org>
2022-08-18 04:00:59 +03:00
spi: spi-amd: Add AMD SPI controller driver support This driver supports SPI Controller for AMD SOCs.This driver supports SPI operations using FIFO mode of transfer. Signed-off-by: Sanjay R Mehta <sanju.mehta@amd.com> Signed-off-by: Mark Brown <broonie@kernel.org> Link: https://lore.kernel.org/r/1587844788-33997-1-git-send-email-sanju.mehta@amd.com Signed-off-by: Mark Brown <broonie@kernel.org>
2020-04-25 14:59:48 -05:00
spi: amd: Setup all xfers before opcode execution The AMD SPI controller hardware seems to expect the FIFO buffer to be fully setup with the details of all transfers in the SPI message before it is able to start processing the data in a reliable way. Furthermore, it imposes a strict ordering restriction, in the sense that all TX transfers must be handled prior any RX transfer. Hence, let's ensure amd_spi_execute_opcode() is called only once, after all TX transfers have been setup, and process any remaining RX transfers afterwards, in a second iteration. Additionally, get rid of the unnecessary AMD_SPI_XFER_TX/RX defines and improve error handling. Signed-off-by: Cristian Ciocaltea <cristian.ciocaltea@collabora.com> Link: https://lore.kernel.org/r/20220818010059.403776-1-cristian.ciocaltea@collabora.com Signed-off-by: Mark Brown <broonie@kernel.org>
2022-08-18 04:00:59 +03:00
spi: spi-amd: Add AMD SPI controller driver support This driver supports SPI Controller for AMD SOCs.This driver supports SPI operations using FIFO mode of transfer. Signed-off-by: Sanjay R Mehta <sanju.mehta@amd.com> Signed-off-by: Mark Brown <broonie@kernel.org> Link: https://lore.kernel.org/r/1587844788-33997-1-git-send-email-sanju.mehta@amd.com Signed-off-by: Mark Brown <broonie@kernel.org>
2020-04-25 14:59:48 -05:00
spi: amd: Setup all xfers before opcode execution The AMD SPI controller hardware seems to expect the FIFO buffer to be fully setup with the details of all transfers in the SPI message before it is able to start processing the data in a reliable way. Furthermore, it imposes a strict ordering restriction, in the sense that all TX transfers must be handled prior any RX transfer. Hence, let's ensure amd_spi_execute_opcode() is called only once, after all TX transfers have been setup, and process any remaining RX transfers afterwards, in a second iteration. Additionally, get rid of the unnecessary AMD_SPI_XFER_TX/RX defines and improve error handling. Signed-off-by: Cristian Ciocaltea <cristian.ciocaltea@collabora.com> Link: https://lore.kernel.org/r/20220818010059.403776-1-cristian.ciocaltea@collabora.com Signed-off-by: Mark Brown <broonie@kernel.org>
2022-08-18 04:00:59 +03:00
spi: spi-amd: Add AMD SPI controller driver support This driver supports SPI Controller for AMD SOCs.This driver supports SPI operations using FIFO mode of transfer. Signed-off-by: Sanjay R Mehta <sanju.mehta@amd.com> Signed-off-by: Mark Brown <broonie@kernel.org> Link: https://lore.kernel.org/r/1587844788-33997-1-git-send-email-sanju.mehta@amd.com Signed-off-by: Mark Brown <broonie@kernel.org>
2020-04-25 14:59:48 -05:00
spi: amd: Setup all xfers before opcode execution The AMD SPI controller hardware seems to expect the FIFO buffer to be fully setup with the details of all transfers in the SPI message before it is able to start processing the data in a reliable way. Furthermore, it imposes a strict ordering restriction, in the sense that all TX transfers must be handled prior any RX transfer. Hence, let's ensure amd_spi_execute_opcode() is called only once, after all TX transfers have been setup, and process any remaining RX transfers afterwards, in a second iteration. Additionally, get rid of the unnecessary AMD_SPI_XFER_TX/RX defines and improve error handling. Signed-off-by: Cristian Ciocaltea <cristian.ciocaltea@collabora.com> Link: https://lore.kernel.org/r/20220818010059.403776-1-cristian.ciocaltea@collabora.com Signed-off-by: Mark Brown <broonie@kernel.org>
2022-08-18 04:00:59 +03:00
spi: spi-amd: Add AMD SPI controller driver support This driver supports SPI Controller for AMD SOCs.This driver supports SPI operations using FIFO mode of transfer. Signed-off-by: Sanjay R Mehta <sanju.mehta@amd.com> Signed-off-by: Mark Brown <broonie@kernel.org> Link: https://lore.kernel.org/r/1587844788-33997-1-git-send-email-sanju.mehta@amd.com Signed-off-by: Mark Brown <broonie@kernel.org>
2020-04-25 14:59:48 -05:00
spi: amd: Add support for version AMDI0062 Add support for the AMD SPI controller version AMDI0062. Do this in a modular way where's easy to add new versions. Signed-off-by: André Almeida <andrealmeid@collabora.com> Link: https://lore.kernel.org/r/20220211143155.75513-4-andrealmeid@collabora.com Signed-off-by: Mark Brown <broonie@kernel.org>
2022-02-11 11:31:55 -03:00
spi: amd: Setup all xfers before opcode execution The AMD SPI controller hardware seems to expect the FIFO buffer to be fully setup with the details of all transfers in the SPI message before it is able to start processing the data in a reliable way. Furthermore, it imposes a strict ordering restriction, in the sense that all TX transfers must be handled prior any RX transfer. Hence, let's ensure amd_spi_execute_opcode() is called only once, after all TX transfers have been setup, and process any remaining RX transfers afterwards, in a second iteration. Additionally, get rid of the unnecessary AMD_SPI_XFER_TX/RX defines and improve error handling. Signed-off-by: Cristian Ciocaltea <cristian.ciocaltea@collabora.com> Link: https://lore.kernel.org/r/20220818010059.403776-1-cristian.ciocaltea@collabora.com Signed-off-by: Mark Brown <broonie@kernel.org>
2022-08-18 04:00:59 +03:00
spi: amd: Add support for version AMDI0062 Add support for the AMD SPI controller version AMDI0062. Do this in a modular way where's easy to add new versions. Signed-off-by: André Almeida <andrealmeid@collabora.com> Link: https://lore.kernel.org/r/20220211143155.75513-4-andrealmeid@collabora.com Signed-off-by: Mark Brown <broonie@kernel.org>
2022-02-11 11:31:55 -03:00
spi: spi_amd: Add support for HID2 SPI controller AMD SoC has HID2 SPI controller in addition to the existing SPI0 controller(AMDI0062). Add HID2 SPI controller's ACPI ID AMDI0063 with its version ID to the list of supported devices. Use the version ID to differentiate the register offsets. And, the AMD HID2 SPI controller supports DMA read, allowing for up to 4 KB of data to be read in single transaction. Update the SPI-MEM support function to reflect this capability. Co-developed-by: Krishnamoorthi M <krishnamoorthi.m@amd.com> Signed-off-by: Krishnamoorthi M <krishnamoorthi.m@amd.com> Co-developed-by: Akshata MukundShetty <akshata.mukundshetty@amd.com> Signed-off-by: Akshata MukundShetty <akshata.mukundshetty@amd.com> Signed-off-by: Raju Rangoju <Raju.Rangoju@amd.com> Link: https://patch.msgid.link/20240925133644.2922359-7-Raju.Rangoju@amd.com Signed-off-by: Mark Brown <broonie@kernel.org>
2024-09-25 19:06:42 +05:30
spi: Replace all spi->chip_select and spi->cs_gpiod references with function call Supporting multi-cs in spi drivers would require the chip_select & cs_gpiod members of struct spi_device to be an array. But changing the type of these members to array would break the spi driver functionality. To make the transition smoother introduced four new APIs to get/set the spi->chip_select & spi->cs_gpiod and replaced all spi->chip_select and spi->cs_gpiod references with get or set API calls. While adding multi-cs support in further patches the chip_select & cs_gpiod members of the spi_device structure would be converted to arrays & the "idx" parameter of the APIs would be used as array index i.e., spi->chip_select[idx] & spi->cs_gpiod[idx] respectively. Signed-off-by: Amit Kumar Mahapatra <amit.kumar-mahapatra@amd.com> Acked-by: Heiko Stuebner <heiko@sntech.de> # Rockchip drivers Reviewed-by: Michal Simek <michal.simek@amd.com> Reviewed-by: Cédric Le Goater <clg@kaod.org> # Aspeed driver Reviewed-by: Dhruva Gole <d-gole@ti.com> # SPI Cadence QSPI Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com> # spi-stm32-qspi Acked-by: William Zhang <william.zhang@broadcom.com> # bcm63xx-hsspi driver Reviewed-by: Serge Semin <fancer.lancer@gmail.com> # DW SSI part Link: https://lore.kernel.org/r/167847070432.26.15076794204368669839@mailman-core.alsa-project.org Signed-off-by: Mark Brown <broonie@kernel.org>
2023-03-10 23:02:03 +05:30
spi: amd: Add support for version AMDI0062 Add support for the AMD SPI controller version AMDI0062. Do this in a modular way where's easy to add new versions. Signed-off-by: André Almeida <andrealmeid@collabora.com> Link: https://lore.kernel.org/r/20220211143155.75513-4-andrealmeid@collabora.com Signed-off-by: Mark Brown <broonie@kernel.org>
2022-02-11 11:31:55 -03:00
spi: amd: switch to use modern name Change legacy name master to modern name host or controller. No functional changed. Signed-off-by: Yang Yingliang <yangyingliang@huawei.com> Link: https://lore.kernel.org/r/20230728093221.3312026-2-yangyingliang@huawei.com Signed-off-by: Mark Brown <broonie@kernel.org>
2023-07-28 17:32:01 +08:00
spi: spi-amd: Add AMD SPI controller driver support This driver supports SPI Controller for AMD SOCs.This driver supports SPI operations using FIFO mode of transfer. Signed-off-by: Sanjay R Mehta <sanju.mehta@amd.com> Signed-off-by: Mark Brown <broonie@kernel.org> Link: https://lore.kernel.org/r/1587844788-33997-1-git-send-email-sanju.mehta@amd.com Signed-off-by: Mark Brown <broonie@kernel.org>
2020-04-25 14:59:48 -05:00
spi: amd: Setup all xfers before opcode execution The AMD SPI controller hardware seems to expect the FIFO buffer to be fully setup with the details of all transfers in the SPI message before it is able to start processing the data in a reliable way. Furthermore, it imposes a strict ordering restriction, in the sense that all TX transfers must be handled prior any RX transfer. Hence, let's ensure amd_spi_execute_opcode() is called only once, after all TX transfers have been setup, and process any remaining RX transfers afterwards, in a second iteration. Additionally, get rid of the unnecessary AMD_SPI_XFER_TX/RX defines and improve error handling. Signed-off-by: Cristian Ciocaltea <cristian.ciocaltea@collabora.com> Link: https://lore.kernel.org/r/20220818010059.403776-1-cristian.ciocaltea@collabora.com Signed-off-by: Mark Brown <broonie@kernel.org>
2022-08-18 04:00:59 +03:00
spi: spi-amd: Add AMD SPI controller driver support This driver supports SPI Controller for AMD SOCs.This driver supports SPI operations using FIFO mode of transfer. Signed-off-by: Sanjay R Mehta <sanju.mehta@amd.com> Signed-off-by: Mark Brown <broonie@kernel.org> Link: https://lore.kernel.org/r/1587844788-33997-1-git-send-email-sanju.mehta@amd.com Signed-off-by: Mark Brown <broonie@kernel.org>
2020-04-25 14:59:48 -05:00
spi: spi_amd: Enable dual and quad I/O modes The current spi_amd driver only supports single I/O mode, despite the AMD SPI controller's capability for dual and quad I/O modes for read operations. And AMD SPI0 controller has limited support for quad mode write operations. Update the SPI-MEM support function to reflect these hardware capabilities. Co-developed-by: Krishnamoorthi M <krishnamoorthi.m@amd.com> Signed-off-by: Krishnamoorthi M <krishnamoorthi.m@amd.com> Co-developed-by: Akshata MukundShetty <akshata.mukundshetty@amd.com> Signed-off-by: Akshata MukundShetty <akshata.mukundshetty@amd.com> Signed-off-by: Raju Rangoju <Raju.Rangoju@amd.com> Link: https://patch.msgid.link/20240925133644.2922359-3-Raju.Rangoju@amd.com Signed-off-by: Mark Brown <broonie@kernel.org>
2024-09-25 19:06:38 +05:30
spi: spi_amd: Add HIDDMA basic write support SPI index mode has hardware limitation of transferring only 64 bytes per transaction due to fixed number of FIFO registers. This constraint leads to performance issues when reading/writing data to/from NAND/NOR flash devices, as the controller must issue multiple requests to read/write 64-byte chunks, even if the slave can transfer up to 2 or 4 KB in a single transaction. The AMD HID2 SPI controller supports DMA mode, allowing for reading/writing up to 4 KB of data in a single transaction. The existing spi_amd driver already supports HID2 DMA read operations. This patch introduces changes to implement HID2 DMA single mode basic write support for the HID2 SPI controller. Co-developed-by: Krishnamoorthi M <krishnamoorthi.m@amd.com> Signed-off-by: Krishnamoorthi M <krishnamoorthi.m@amd.com> Co-developed-by: Akshata MukundShetty <akshata.mukundshetty@amd.com> Signed-off-by: Akshata MukundShetty <akshata.mukundshetty@amd.com> Signed-off-by: Raju Rangoju <Raju.Rangoju@amd.com> Link: https://patch.msgid.link/20250516100658.585654-3-Raju.Rangoju@amd.com Signed-off-by: Mark Brown <broonie@kernel.org>
2025-05-16 15:36:57 +05:30
spi: spi_amd: Add support for SPI MEM framework Add support to the SPI controller driver to use SPI MEM framework. SPI subsystem utilizing the SPI memory operations allows to re-use SPI controller drivers for both SPI NOR devices, regular SPI devices as well as SPI NAND devices. Add below functions of spi_mem_ops to support SPI MEM framework - exec-op(): to execute the memory operations. - supports_op(): to check if the memory operation is supported. - adjust_op_size(): to split data transfers so that they don’t exceed the max transfer size supported by the controller. Suggested-by: Sudheesh Mavila <sudheesh.mavila@amd.com> Co-developed-by: Krishnamoorthi M <krishnamoorthi.m@amd.com> Signed-off-by: Krishnamoorthi M <krishnamoorthi.m@amd.com> Co-developed-by: Akshata MukundShetty <akshata.mukundshetty@amd.com> Signed-off-by: Akshata MukundShetty <akshata.mukundshetty@amd.com> Signed-off-by: Raju Rangoju <Raju.Rangoju@amd.com> Link: https://msgid.link/r/20240229134544.3461757-1-Raju.Rangoju@amd.com Signed-off-by: Mark Brown <broonie@kernel.org>
2024-02-29 19:15:44 +05:30
spi: spi_amd: Add support for HID2 SPI controller AMD SoC has HID2 SPI controller in addition to the existing SPI0 controller(AMDI0062). Add HID2 SPI controller's ACPI ID AMDI0063 with its version ID to the list of supported devices. Use the version ID to differentiate the register offsets. And, the AMD HID2 SPI controller supports DMA read, allowing for up to 4 KB of data to be read in single transaction. Update the SPI-MEM support function to reflect this capability. Co-developed-by: Krishnamoorthi M <krishnamoorthi.m@amd.com> Signed-off-by: Krishnamoorthi M <krishnamoorthi.m@amd.com> Co-developed-by: Akshata MukundShetty <akshata.mukundshetty@amd.com> Signed-off-by: Akshata MukundShetty <akshata.mukundshetty@amd.com> Signed-off-by: Raju Rangoju <Raju.Rangoju@amd.com> Link: https://patch.msgid.link/20240925133644.2922359-7-Raju.Rangoju@amd.com Signed-off-by: Mark Brown <broonie@kernel.org>
2024-09-25 19:06:42 +05:30
spi: spi_amd: Add support for SPI MEM framework Add support to the SPI controller driver to use SPI MEM framework. SPI subsystem utilizing the SPI memory operations allows to re-use SPI controller drivers for both SPI NOR devices, regular SPI devices as well as SPI NAND devices. Add below functions of spi_mem_ops to support SPI MEM framework - exec-op(): to execute the memory operations. - supports_op(): to check if the memory operation is supported. - adjust_op_size(): to split data transfers so that they don’t exceed the max transfer size supported by the controller. Suggested-by: Sudheesh Mavila <sudheesh.mavila@amd.com> Co-developed-by: Krishnamoorthi M <krishnamoorthi.m@amd.com> Signed-off-by: Krishnamoorthi M <krishnamoorthi.m@amd.com> Co-developed-by: Akshata MukundShetty <akshata.mukundshetty@amd.com> Signed-off-by: Akshata MukundShetty <akshata.mukundshetty@amd.com> Signed-off-by: Raju Rangoju <Raju.Rangoju@amd.com> Link: https://msgid.link/r/20240229134544.3461757-1-Raju.Rangoju@amd.com Signed-off-by: Mark Brown <broonie@kernel.org>
2024-02-29 19:15:44 +05:30
spi: spi_amd: Add support for HID2 SPI controller AMD SoC has HID2 SPI controller in addition to the existing SPI0 controller(AMDI0062). Add HID2 SPI controller's ACPI ID AMDI0063 with its version ID to the list of supported devices. Use the version ID to differentiate the register offsets. And, the AMD HID2 SPI controller supports DMA read, allowing for up to 4 KB of data to be read in single transaction. Update the SPI-MEM support function to reflect this capability. Co-developed-by: Krishnamoorthi M <krishnamoorthi.m@amd.com> Signed-off-by: Krishnamoorthi M <krishnamoorthi.m@amd.com> Co-developed-by: Akshata MukundShetty <akshata.mukundshetty@amd.com> Signed-off-by: Akshata MukundShetty <akshata.mukundshetty@amd.com> Signed-off-by: Raju Rangoju <Raju.Rangoju@amd.com> Link: https://patch.msgid.link/20240925133644.2922359-7-Raju.Rangoju@amd.com Signed-off-by: Mark Brown <broonie@kernel.org>
2024-09-25 19:06:42 +05:30
spi: spi_amd: Add support for SPI MEM framework Add support to the SPI controller driver to use SPI MEM framework. SPI subsystem utilizing the SPI memory operations allows to re-use SPI controller drivers for both SPI NOR devices, regular SPI devices as well as SPI NAND devices. Add below functions of spi_mem_ops to support SPI MEM framework - exec-op(): to execute the memory operations. - supports_op(): to check if the memory operation is supported. - adjust_op_size(): to split data transfers so that they don’t exceed the max transfer size supported by the controller. Suggested-by: Sudheesh Mavila <sudheesh.mavila@amd.com> Co-developed-by: Krishnamoorthi M <krishnamoorthi.m@amd.com> Signed-off-by: Krishnamoorthi M <krishnamoorthi.m@amd.com> Co-developed-by: Akshata MukundShetty <akshata.mukundshetty@amd.com> Signed-off-by: Akshata MukundShetty <akshata.mukundshetty@amd.com> Signed-off-by: Raju Rangoju <Raju.Rangoju@amd.com> Link: https://msgid.link/r/20240229134544.3461757-1-Raju.Rangoju@amd.com Signed-off-by: Mark Brown <broonie@kernel.org>
2024-02-29 19:15:44 +05:30
spi: spi_amd: Enable dual and quad I/O modes The current spi_amd driver only supports single I/O mode, despite the AMD SPI controller's capability for dual and quad I/O modes for read operations. And AMD SPI0 controller has limited support for quad mode write operations. Update the SPI-MEM support function to reflect these hardware capabilities. Co-developed-by: Krishnamoorthi M <krishnamoorthi.m@amd.com> Signed-off-by: Krishnamoorthi M <krishnamoorthi.m@amd.com> Co-developed-by: Akshata MukundShetty <akshata.mukundshetty@amd.com> Signed-off-by: Akshata MukundShetty <akshata.mukundshetty@amd.com> Signed-off-by: Raju Rangoju <Raju.Rangoju@amd.com> Link: https://patch.msgid.link/20240925133644.2922359-3-Raju.Rangoju@amd.com Signed-off-by: Mark Brown <broonie@kernel.org>
2024-09-25 19:06:38 +05:30
spi: spi_amd: Add HIDDMA basic write support SPI index mode has hardware limitation of transferring only 64 bytes per transaction due to fixed number of FIFO registers. This constraint leads to performance issues when reading/writing data to/from NAND/NOR flash devices, as the controller must issue multiple requests to read/write 64-byte chunks, even if the slave can transfer up to 2 or 4 KB in a single transaction. The AMD HID2 SPI controller supports DMA mode, allowing for reading/writing up to 4 KB of data in a single transaction. The existing spi_amd driver already supports HID2 DMA read operations. This patch introduces changes to implement HID2 DMA single mode basic write support for the HID2 SPI controller. Co-developed-by: Krishnamoorthi M <krishnamoorthi.m@amd.com> Signed-off-by: Krishnamoorthi M <krishnamoorthi.m@amd.com> Co-developed-by: Akshata MukundShetty <akshata.mukundshetty@amd.com> Signed-off-by: Akshata MukundShetty <akshata.mukundshetty@amd.com> Signed-off-by: Raju Rangoju <Raju.Rangoju@amd.com> Link: https://patch.msgid.link/20250516100658.585654-3-Raju.Rangoju@amd.com Signed-off-by: Mark Brown <broonie@kernel.org>
2025-05-16 15:36:57 +05:30
spi: spi_amd: Enable dual and quad I/O modes The current spi_amd driver only supports single I/O mode, despite the AMD SPI controller's capability for dual and quad I/O modes for read operations. And AMD SPI0 controller has limited support for quad mode write operations. Update the SPI-MEM support function to reflect these hardware capabilities. Co-developed-by: Krishnamoorthi M <krishnamoorthi.m@amd.com> Signed-off-by: Krishnamoorthi M <krishnamoorthi.m@amd.com> Co-developed-by: Akshata MukundShetty <akshata.mukundshetty@amd.com> Signed-off-by: Akshata MukundShetty <akshata.mukundshetty@amd.com> Signed-off-by: Raju Rangoju <Raju.Rangoju@amd.com> Link: https://patch.msgid.link/20240925133644.2922359-3-Raju.Rangoju@amd.com Signed-off-by: Mark Brown <broonie@kernel.org>
2024-09-25 19:06:38 +05:30
spi: spi_amd: Add support for HID2 SPI controller AMD SoC has HID2 SPI controller in addition to the existing SPI0 controller(AMDI0062). Add HID2 SPI controller's ACPI ID AMDI0063 with its version ID to the list of supported devices. Use the version ID to differentiate the register offsets. And, the AMD HID2 SPI controller supports DMA read, allowing for up to 4 KB of data to be read in single transaction. Update the SPI-MEM support function to reflect this capability. Co-developed-by: Krishnamoorthi M <krishnamoorthi.m@amd.com> Signed-off-by: Krishnamoorthi M <krishnamoorthi.m@amd.com> Co-developed-by: Akshata MukundShetty <akshata.mukundshetty@amd.com> Signed-off-by: Akshata MukundShetty <akshata.mukundshetty@amd.com> Signed-off-by: Raju Rangoju <Raju.Rangoju@amd.com> Link: https://patch.msgid.link/20240925133644.2922359-7-Raju.Rangoju@amd.com Signed-off-by: Mark Brown <broonie@kernel.org>
2024-09-25 19:06:42 +05:30
spi: spi_amd: Add HIDDMA basic write support SPI index mode has hardware limitation of transferring only 64 bytes per transaction due to fixed number of FIFO registers. This constraint leads to performance issues when reading/writing data to/from NAND/NOR flash devices, as the controller must issue multiple requests to read/write 64-byte chunks, even if the slave can transfer up to 2 or 4 KB in a single transaction. The AMD HID2 SPI controller supports DMA mode, allowing for reading/writing up to 4 KB of data in a single transaction. The existing spi_amd driver already supports HID2 DMA read operations. This patch introduces changes to implement HID2 DMA single mode basic write support for the HID2 SPI controller. Co-developed-by: Krishnamoorthi M <krishnamoorthi.m@amd.com> Signed-off-by: Krishnamoorthi M <krishnamoorthi.m@amd.com> Co-developed-by: Akshata MukundShetty <akshata.mukundshetty@amd.com> Signed-off-by: Akshata MukundShetty <akshata.mukundshetty@amd.com> Signed-off-by: Raju Rangoju <Raju.Rangoju@amd.com> Link: https://patch.msgid.link/20250516100658.585654-3-Raju.Rangoju@amd.com Signed-off-by: Mark Brown <broonie@kernel.org>
2025-05-16 15:36:57 +05:30
spi: spi_amd: Add support for HID2 SPI controller AMD SoC has HID2 SPI controller in addition to the existing SPI0 controller(AMDI0062). Add HID2 SPI controller's ACPI ID AMDI0063 with its version ID to the list of supported devices. Use the version ID to differentiate the register offsets. And, the AMD HID2 SPI controller supports DMA read, allowing for up to 4 KB of data to be read in single transaction. Update the SPI-MEM support function to reflect this capability. Co-developed-by: Krishnamoorthi M <krishnamoorthi.m@amd.com> Signed-off-by: Krishnamoorthi M <krishnamoorthi.m@amd.com> Co-developed-by: Akshata MukundShetty <akshata.mukundshetty@amd.com> Signed-off-by: Akshata MukundShetty <akshata.mukundshetty@amd.com> Signed-off-by: Raju Rangoju <Raju.Rangoju@amd.com> Link: https://patch.msgid.link/20240925133644.2922359-7-Raju.Rangoju@amd.com Signed-off-by: Mark Brown <broonie@kernel.org>
2024-09-25 19:06:42 +05:30
spi: spi_amd: Enable dual and quad I/O modes The current spi_amd driver only supports single I/O mode, despite the AMD SPI controller's capability for dual and quad I/O modes for read operations. And AMD SPI0 controller has limited support for quad mode write operations. Update the SPI-MEM support function to reflect these hardware capabilities. Co-developed-by: Krishnamoorthi M <krishnamoorthi.m@amd.com> Signed-off-by: Krishnamoorthi M <krishnamoorthi.m@amd.com> Co-developed-by: Akshata MukundShetty <akshata.mukundshetty@amd.com> Signed-off-by: Akshata MukundShetty <akshata.mukundshetty@amd.com> Signed-off-by: Raju Rangoju <Raju.Rangoju@amd.com> Link: https://patch.msgid.link/20240925133644.2922359-3-Raju.Rangoju@amd.com Signed-off-by: Mark Brown <broonie@kernel.org>
2024-09-25 19:06:38 +05:30
spi: amd: Support per spi-mem operation frequency switches Every ->exec_op() call correctly configures the spi bus speed to the maximum allowed frequency for the memory using the constant spi default parameter. Since we can now have per-operation constraints, let's use the value that comes from the spi-mem operation structure instead. In case there is no specific limitation for this operation, the default spi device value will be given anyway. This controller however performed a frequency check, which is also observed during the ->check_op() phase. The per-operation frequency capability is thus advertised to the spi-mem core. Cc: Sanjay R Mehta <sanju.mehta@amd.com> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> Link: https://patch.msgid.link/20241224-winbond-6-11-rc1-quad-support-v2-3-ad218dbc406f@bootlin.com Signed-off-by: Mark Brown <broonie@kernel.org>
2024-12-24 18:05:48 +01:00
spi: spi_amd: Add support for SPI MEM framework Add support to the SPI controller driver to use SPI MEM framework. SPI subsystem utilizing the SPI memory operations allows to re-use SPI controller drivers for both SPI NOR devices, regular SPI devices as well as SPI NAND devices. Add below functions of spi_mem_ops to support SPI MEM framework - exec-op(): to execute the memory operations. - supports_op(): to check if the memory operation is supported. - adjust_op_size(): to split data transfers so that they don’t exceed the max transfer size supported by the controller. Suggested-by: Sudheesh Mavila <sudheesh.mavila@amd.com> Co-developed-by: Krishnamoorthi M <krishnamoorthi.m@amd.com> Signed-off-by: Krishnamoorthi M <krishnamoorthi.m@amd.com> Co-developed-by: Akshata MukundShetty <akshata.mukundshetty@amd.com> Signed-off-by: Akshata MukundShetty <akshata.mukundshetty@amd.com> Signed-off-by: Raju Rangoju <Raju.Rangoju@amd.com> Link: https://msgid.link/r/20240229134544.3461757-1-Raju.Rangoju@amd.com Signed-off-by: Mark Brown <broonie@kernel.org>
2024-02-29 19:15:44 +05:30
spi: spi_amd: Add support for HID2 SPI controller AMD SoC has HID2 SPI controller in addition to the existing SPI0 controller(AMDI0062). Add HID2 SPI controller's ACPI ID AMDI0063 with its version ID to the list of supported devices. Use the version ID to differentiate the register offsets. And, the AMD HID2 SPI controller supports DMA read, allowing for up to 4 KB of data to be read in single transaction. Update the SPI-MEM support function to reflect this capability. Co-developed-by: Krishnamoorthi M <krishnamoorthi.m@amd.com> Signed-off-by: Krishnamoorthi M <krishnamoorthi.m@amd.com> Co-developed-by: Akshata MukundShetty <akshata.mukundshetty@amd.com> Signed-off-by: Akshata MukundShetty <akshata.mukundshetty@amd.com> Signed-off-by: Raju Rangoju <Raju.Rangoju@amd.com> Link: https://patch.msgid.link/20240925133644.2922359-7-Raju.Rangoju@amd.com Signed-off-by: Mark Brown <broonie@kernel.org>
2024-09-25 19:06:42 +05:30
spi: spi_amd: Add HIDDMA basic write support SPI index mode has hardware limitation of transferring only 64 bytes per transaction due to fixed number of FIFO registers. This constraint leads to performance issues when reading/writing data to/from NAND/NOR flash devices, as the controller must issue multiple requests to read/write 64-byte chunks, even if the slave can transfer up to 2 or 4 KB in a single transaction. The AMD HID2 SPI controller supports DMA mode, allowing for reading/writing up to 4 KB of data in a single transaction. The existing spi_amd driver already supports HID2 DMA read operations. This patch introduces changes to implement HID2 DMA single mode basic write support for the HID2 SPI controller. Co-developed-by: Krishnamoorthi M <krishnamoorthi.m@amd.com> Signed-off-by: Krishnamoorthi M <krishnamoorthi.m@amd.com> Co-developed-by: Akshata MukundShetty <akshata.mukundshetty@amd.com> Signed-off-by: Akshata MukundShetty <akshata.mukundshetty@amd.com> Signed-off-by: Raju Rangoju <Raju.Rangoju@amd.com> Link: https://patch.msgid.link/20250516100658.585654-3-Raju.Rangoju@amd.com Signed-off-by: Mark Brown <broonie@kernel.org>
2025-05-16 15:36:57 +05:30
spi: spi_amd: Add support for HID2 SPI controller AMD SoC has HID2 SPI controller in addition to the existing SPI0 controller(AMDI0062). Add HID2 SPI controller's ACPI ID AMDI0063 with its version ID to the list of supported devices. Use the version ID to differentiate the register offsets. And, the AMD HID2 SPI controller supports DMA read, allowing for up to 4 KB of data to be read in single transaction. Update the SPI-MEM support function to reflect this capability. Co-developed-by: Krishnamoorthi M <krishnamoorthi.m@amd.com> Signed-off-by: Krishnamoorthi M <krishnamoorthi.m@amd.com> Co-developed-by: Akshata MukundShetty <akshata.mukundshetty@amd.com> Signed-off-by: Akshata MukundShetty <akshata.mukundshetty@amd.com> Signed-off-by: Raju Rangoju <Raju.Rangoju@amd.com> Link: https://patch.msgid.link/20240925133644.2922359-7-Raju.Rangoju@amd.com Signed-off-by: Mark Brown <broonie@kernel.org>
2024-09-25 19:06:42 +05:30
spi: spi_amd: Add support for SPI MEM framework Add support to the SPI controller driver to use SPI MEM framework. SPI subsystem utilizing the SPI memory operations allows to re-use SPI controller drivers for both SPI NOR devices, regular SPI devices as well as SPI NAND devices. Add below functions of spi_mem_ops to support SPI MEM framework - exec-op(): to execute the memory operations. - supports_op(): to check if the memory operation is supported. - adjust_op_size(): to split data transfers so that they don’t exceed the max transfer size supported by the controller. Suggested-by: Sudheesh Mavila <sudheesh.mavila@amd.com> Co-developed-by: Krishnamoorthi M <krishnamoorthi.m@amd.com> Signed-off-by: Krishnamoorthi M <krishnamoorthi.m@amd.com> Co-developed-by: Akshata MukundShetty <akshata.mukundshetty@amd.com> Signed-off-by: Akshata MukundShetty <akshata.mukundshetty@amd.com> Signed-off-by: Raju Rangoju <Raju.Rangoju@amd.com> Link: https://msgid.link/r/20240229134544.3461757-1-Raju.Rangoju@amd.com Signed-off-by: Mark Brown <broonie@kernel.org>
2024-02-29 19:15:44 +05:30
spi: spi_amd: Add HIDDMA basic write support SPI index mode has hardware limitation of transferring only 64 bytes per transaction due to fixed number of FIFO registers. This constraint leads to performance issues when reading/writing data to/from NAND/NOR flash devices, as the controller must issue multiple requests to read/write 64-byte chunks, even if the slave can transfer up to 2 or 4 KB in a single transaction. The AMD HID2 SPI controller supports DMA mode, allowing for reading/writing up to 4 KB of data in a single transaction. The existing spi_amd driver already supports HID2 DMA read operations. This patch introduces changes to implement HID2 DMA single mode basic write support for the HID2 SPI controller. Co-developed-by: Krishnamoorthi M <krishnamoorthi.m@amd.com> Signed-off-by: Krishnamoorthi M <krishnamoorthi.m@amd.com> Co-developed-by: Akshata MukundShetty <akshata.mukundshetty@amd.com> Signed-off-by: Akshata MukundShetty <akshata.mukundshetty@amd.com> Signed-off-by: Raju Rangoju <Raju.Rangoju@amd.com> Link: https://patch.msgid.link/20250516100658.585654-3-Raju.Rangoju@amd.com Signed-off-by: Mark Brown <broonie@kernel.org>
2025-05-16 15:36:57 +05:30
spi: spi_amd: Add support for SPI MEM framework Add support to the SPI controller driver to use SPI MEM framework. SPI subsystem utilizing the SPI memory operations allows to re-use SPI controller drivers for both SPI NOR devices, regular SPI devices as well as SPI NAND devices. Add below functions of spi_mem_ops to support SPI MEM framework - exec-op(): to execute the memory operations. - supports_op(): to check if the memory operation is supported. - adjust_op_size(): to split data transfers so that they don’t exceed the max transfer size supported by the controller. Suggested-by: Sudheesh Mavila <sudheesh.mavila@amd.com> Co-developed-by: Krishnamoorthi M <krishnamoorthi.m@amd.com> Signed-off-by: Krishnamoorthi M <krishnamoorthi.m@amd.com> Co-developed-by: Akshata MukundShetty <akshata.mukundshetty@amd.com> Signed-off-by: Akshata MukundShetty <akshata.mukundshetty@amd.com> Signed-off-by: Raju Rangoju <Raju.Rangoju@amd.com> Link: https://msgid.link/r/20240229134544.3461757-1-Raju.Rangoju@amd.com Signed-off-by: Mark Brown <broonie@kernel.org>
2024-02-29 19:15:44 +05:30
spi: spi_amd: Optimize IO operations Read and write the maximum number of data bytes at once, rather than byte by byte. This improves AMD SPI controller driver performance by reducing the time required to access FIFO registers. For example, with the new changes, 64 bytes of data from the FIFO queue can be read in 8 read calls (8 bytes per call) instead of 64 read calls(1 byte per call). Co-developed-by: Krishnamoorthi M <krishnamoorthi.m@amd.com> Signed-off-by: Krishnamoorthi M <krishnamoorthi.m@amd.com> Co-developed-by: Akshata MukundShetty <akshata.mukundshetty@amd.com> Signed-off-by: Akshata MukundShetty <akshata.mukundshetty@amd.com> Signed-off-by: Raju Rangoju <Raju.Rangoju@amd.com> Link: https://patch.msgid.link/20240925133644.2922359-6-Raju.Rangoju@amd.com Signed-off-by: Mark Brown <broonie@kernel.org>
2024-09-25 19:06:41 +05:30
spi: spi_amd: Add HIDDMA basic write support SPI index mode has hardware limitation of transferring only 64 bytes per transaction due to fixed number of FIFO registers. This constraint leads to performance issues when reading/writing data to/from NAND/NOR flash devices, as the controller must issue multiple requests to read/write 64-byte chunks, even if the slave can transfer up to 2 or 4 KB in a single transaction. The AMD HID2 SPI controller supports DMA mode, allowing for reading/writing up to 4 KB of data in a single transaction. The existing spi_amd driver already supports HID2 DMA read operations. This patch introduces changes to implement HID2 DMA single mode basic write support for the HID2 SPI controller. Co-developed-by: Krishnamoorthi M <krishnamoorthi.m@amd.com> Signed-off-by: Krishnamoorthi M <krishnamoorthi.m@amd.com> Co-developed-by: Akshata MukundShetty <akshata.mukundshetty@amd.com> Signed-off-by: Akshata MukundShetty <akshata.mukundshetty@amd.com> Signed-off-by: Raju Rangoju <Raju.Rangoju@amd.com> Link: https://patch.msgid.link/20250516100658.585654-3-Raju.Rangoju@amd.com Signed-off-by: Mark Brown <broonie@kernel.org>
2025-05-16 15:36:57 +05:30
spi: spi_amd: Add support for SPI MEM framework Add support to the SPI controller driver to use SPI MEM framework. SPI subsystem utilizing the SPI memory operations allows to re-use SPI controller drivers for both SPI NOR devices, regular SPI devices as well as SPI NAND devices. Add below functions of spi_mem_ops to support SPI MEM framework - exec-op(): to execute the memory operations. - supports_op(): to check if the memory operation is supported. - adjust_op_size(): to split data transfers so that they don’t exceed the max transfer size supported by the controller. Suggested-by: Sudheesh Mavila <sudheesh.mavila@amd.com> Co-developed-by: Krishnamoorthi M <krishnamoorthi.m@amd.com> Signed-off-by: Krishnamoorthi M <krishnamoorthi.m@amd.com> Co-developed-by: Akshata MukundShetty <akshata.mukundshetty@amd.com> Signed-off-by: Akshata MukundShetty <akshata.mukundshetty@amd.com> Signed-off-by: Raju Rangoju <Raju.Rangoju@amd.com> Link: https://msgid.link/r/20240229134544.3461757-1-Raju.Rangoju@amd.com Signed-off-by: Mark Brown <broonie@kernel.org>
2024-02-29 19:15:44 +05:30
spi: spi_amd: Optimize IO operations Read and write the maximum number of data bytes at once, rather than byte by byte. This improves AMD SPI controller driver performance by reducing the time required to access FIFO registers. For example, with the new changes, 64 bytes of data from the FIFO queue can be read in 8 read calls (8 bytes per call) instead of 64 read calls(1 byte per call). Co-developed-by: Krishnamoorthi M <krishnamoorthi.m@amd.com> Signed-off-by: Krishnamoorthi M <krishnamoorthi.m@amd.com> Co-developed-by: Akshata MukundShetty <akshata.mukundshetty@amd.com> Signed-off-by: Akshata MukundShetty <akshata.mukundshetty@amd.com> Signed-off-by: Raju Rangoju <Raju.Rangoju@amd.com> Link: https://patch.msgid.link/20240925133644.2922359-6-Raju.Rangoju@amd.com Signed-off-by: Mark Brown <broonie@kernel.org>
2024-09-25 19:06:41 +05:30
spi: spi_amd: Add support for SPI MEM framework Add support to the SPI controller driver to use SPI MEM framework. SPI subsystem utilizing the SPI memory operations allows to re-use SPI controller drivers for both SPI NOR devices, regular SPI devices as well as SPI NAND devices. Add below functions of spi_mem_ops to support SPI MEM framework - exec-op(): to execute the memory operations. - supports_op(): to check if the memory operation is supported. - adjust_op_size(): to split data transfers so that they don’t exceed the max transfer size supported by the controller. Suggested-by: Sudheesh Mavila <sudheesh.mavila@amd.com> Co-developed-by: Krishnamoorthi M <krishnamoorthi.m@amd.com> Signed-off-by: Krishnamoorthi M <krishnamoorthi.m@amd.com> Co-developed-by: Akshata MukundShetty <akshata.mukundshetty@amd.com> Signed-off-by: Akshata MukundShetty <akshata.mukundshetty@amd.com> Signed-off-by: Raju Rangoju <Raju.Rangoju@amd.com> Link: https://msgid.link/r/20240229134544.3461757-1-Raju.Rangoju@amd.com Signed-off-by: Mark Brown <broonie@kernel.org>
2024-02-29 19:15:44 +05:30
spi: spi_amd: Add HIDDMA basic write support SPI index mode has hardware limitation of transferring only 64 bytes per transaction due to fixed number of FIFO registers. This constraint leads to performance issues when reading/writing data to/from NAND/NOR flash devices, as the controller must issue multiple requests to read/write 64-byte chunks, even if the slave can transfer up to 2 or 4 KB in a single transaction. The AMD HID2 SPI controller supports DMA mode, allowing for reading/writing up to 4 KB of data in a single transaction. The existing spi_amd driver already supports HID2 DMA read operations. This patch introduces changes to implement HID2 DMA single mode basic write support for the HID2 SPI controller. Co-developed-by: Krishnamoorthi M <krishnamoorthi.m@amd.com> Signed-off-by: Krishnamoorthi M <krishnamoorthi.m@amd.com> Co-developed-by: Akshata MukundShetty <akshata.mukundshetty@amd.com> Signed-off-by: Akshata MukundShetty <akshata.mukundshetty@amd.com> Signed-off-by: Raju Rangoju <Raju.Rangoju@amd.com> Link: https://patch.msgid.link/20250516100658.585654-3-Raju.Rangoju@amd.com Signed-off-by: Mark Brown <broonie@kernel.org>
2025-05-16 15:36:57 +05:30
spi: spi_amd: Add support for SPI MEM framework Add support to the SPI controller driver to use SPI MEM framework. SPI subsystem utilizing the SPI memory operations allows to re-use SPI controller drivers for both SPI NOR devices, regular SPI devices as well as SPI NAND devices. Add below functions of spi_mem_ops to support SPI MEM framework - exec-op(): to execute the memory operations. - supports_op(): to check if the memory operation is supported. - adjust_op_size(): to split data transfers so that they don’t exceed the max transfer size supported by the controller. Suggested-by: Sudheesh Mavila <sudheesh.mavila@amd.com> Co-developed-by: Krishnamoorthi M <krishnamoorthi.m@amd.com> Signed-off-by: Krishnamoorthi M <krishnamoorthi.m@amd.com> Co-developed-by: Akshata MukundShetty <akshata.mukundshetty@amd.com> Signed-off-by: Akshata MukundShetty <akshata.mukundshetty@amd.com> Signed-off-by: Raju Rangoju <Raju.Rangoju@amd.com> Link: https://msgid.link/r/20240229134544.3461757-1-Raju.Rangoju@amd.com Signed-off-by: Mark Brown <broonie@kernel.org>
2024-02-29 19:15:44 +05:30
spi: spi_amd: Add HIDDMA basic write support SPI index mode has hardware limitation of transferring only 64 bytes per transaction due to fixed number of FIFO registers. This constraint leads to performance issues when reading/writing data to/from NAND/NOR flash devices, as the controller must issue multiple requests to read/write 64-byte chunks, even if the slave can transfer up to 2 or 4 KB in a single transaction. The AMD HID2 SPI controller supports DMA mode, allowing for reading/writing up to 4 KB of data in a single transaction. The existing spi_amd driver already supports HID2 DMA read operations. This patch introduces changes to implement HID2 DMA single mode basic write support for the HID2 SPI controller. Co-developed-by: Krishnamoorthi M <krishnamoorthi.m@amd.com> Signed-off-by: Krishnamoorthi M <krishnamoorthi.m@amd.com> Co-developed-by: Akshata MukundShetty <akshata.mukundshetty@amd.com> Signed-off-by: Akshata MukundShetty <akshata.mukundshetty@amd.com> Signed-off-by: Raju Rangoju <Raju.Rangoju@amd.com> Link: https://patch.msgid.link/20250516100658.585654-3-Raju.Rangoju@amd.com Signed-off-by: Mark Brown <broonie@kernel.org>
2025-05-16 15:36:57 +05:30
spi: spi_amd: Optimize IO operations Read and write the maximum number of data bytes at once, rather than byte by byte. This improves AMD SPI controller driver performance by reducing the time required to access FIFO registers. For example, with the new changes, 64 bytes of data from the FIFO queue can be read in 8 read calls (8 bytes per call) instead of 64 read calls(1 byte per call). Co-developed-by: Krishnamoorthi M <krishnamoorthi.m@amd.com> Signed-off-by: Krishnamoorthi M <krishnamoorthi.m@amd.com> Co-developed-by: Akshata MukundShetty <akshata.mukundshetty@amd.com> Signed-off-by: Akshata MukundShetty <akshata.mukundshetty@amd.com> Signed-off-by: Raju Rangoju <Raju.Rangoju@amd.com> Link: https://patch.msgid.link/20240925133644.2922359-6-Raju.Rangoju@amd.com Signed-off-by: Mark Brown <broonie@kernel.org>
2024-09-25 19:06:41 +05:30
spi: spi_amd: Add HIDDMA basic write support SPI index mode has hardware limitation of transferring only 64 bytes per transaction due to fixed number of FIFO registers. This constraint leads to performance issues when reading/writing data to/from NAND/NOR flash devices, as the controller must issue multiple requests to read/write 64-byte chunks, even if the slave can transfer up to 2 or 4 KB in a single transaction. The AMD HID2 SPI controller supports DMA mode, allowing for reading/writing up to 4 KB of data in a single transaction. The existing spi_amd driver already supports HID2 DMA read operations. This patch introduces changes to implement HID2 DMA single mode basic write support for the HID2 SPI controller. Co-developed-by: Krishnamoorthi M <krishnamoorthi.m@amd.com> Signed-off-by: Krishnamoorthi M <krishnamoorthi.m@amd.com> Co-developed-by: Akshata MukundShetty <akshata.mukundshetty@amd.com> Signed-off-by: Akshata MukundShetty <akshata.mukundshetty@amd.com> Signed-off-by: Raju Rangoju <Raju.Rangoju@amd.com> Link: https://patch.msgid.link/20250516100658.585654-3-Raju.Rangoju@amd.com Signed-off-by: Mark Brown <broonie@kernel.org>
2025-05-16 15:36:57 +05:30
spi: spi_amd: Optimize IO operations Read and write the maximum number of data bytes at once, rather than byte by byte. This improves AMD SPI controller driver performance by reducing the time required to access FIFO registers. For example, with the new changes, 64 bytes of data from the FIFO queue can be read in 8 read calls (8 bytes per call) instead of 64 read calls(1 byte per call). Co-developed-by: Krishnamoorthi M <krishnamoorthi.m@amd.com> Signed-off-by: Krishnamoorthi M <krishnamoorthi.m@amd.com> Co-developed-by: Akshata MukundShetty <akshata.mukundshetty@amd.com> Signed-off-by: Akshata MukundShetty <akshata.mukundshetty@amd.com> Signed-off-by: Raju Rangoju <Raju.Rangoju@amd.com> Link: https://patch.msgid.link/20240925133644.2922359-6-Raju.Rangoju@amd.com Signed-off-by: Mark Brown <broonie@kernel.org>
2024-09-25 19:06:41 +05:30
spi: spi_amd: Add support for SPI MEM framework Add support to the SPI controller driver to use SPI MEM framework. SPI subsystem utilizing the SPI memory operations allows to re-use SPI controller drivers for both SPI NOR devices, regular SPI devices as well as SPI NAND devices. Add below functions of spi_mem_ops to support SPI MEM framework - exec-op(): to execute the memory operations. - supports_op(): to check if the memory operation is supported. - adjust_op_size(): to split data transfers so that they don’t exceed the max transfer size supported by the controller. Suggested-by: Sudheesh Mavila <sudheesh.mavila@amd.com> Co-developed-by: Krishnamoorthi M <krishnamoorthi.m@amd.com> Signed-off-by: Krishnamoorthi M <krishnamoorthi.m@amd.com> Co-developed-by: Akshata MukundShetty <akshata.mukundshetty@amd.com> Signed-off-by: Akshata MukundShetty <akshata.mukundshetty@amd.com> Signed-off-by: Raju Rangoju <Raju.Rangoju@amd.com> Link: https://msgid.link/r/20240229134544.3461757-1-Raju.Rangoju@amd.com Signed-off-by: Mark Brown <broonie@kernel.org>
2024-02-29 19:15:44 +05:30
spi: spi_amd: Add HIDDMA basic read support SPI index mode has hardware limitation of reading only 64 bytes per transaction due to fixed number of FIFO registers. This constraint leads to performance issues when reading data from NAND/NOR flash devices, as the controller must issue multiple requests to read 64-byte chunks, even if the slave can send up to 2 or 4 KB in single transaction. The AMD HID2 SPI controller supports DMA mode, which allows reading up to 4 KB of data in single transaction. This patch introduces changes to implement HID2 DMA read support for the HID2 SPI controller. Co-developed-by: Krishnamoorthi M <krishnamoorthi.m@amd.com> Signed-off-by: Krishnamoorthi M <krishnamoorthi.m@amd.com> Co-developed-by: Akshata MukundShetty <akshata.mukundshetty@amd.com> Signed-off-by: Akshata MukundShetty <akshata.mukundshetty@amd.com> Signed-off-by: Raju Rangoju <Raju.Rangoju@amd.com> Link: https://patch.msgid.link/20240925133644.2922359-9-Raju.Rangoju@amd.com Signed-off-by: Mark Brown <broonie@kernel.org>
2024-09-25 19:06:44 +05:30
spi: spi_amd: Add support for SPI MEM framework Add support to the SPI controller driver to use SPI MEM framework. SPI subsystem utilizing the SPI memory operations allows to re-use SPI controller drivers for both SPI NOR devices, regular SPI devices as well as SPI NAND devices. Add below functions of spi_mem_ops to support SPI MEM framework - exec-op(): to execute the memory operations. - supports_op(): to check if the memory operation is supported. - adjust_op_size(): to split data transfers so that they don’t exceed the max transfer size supported by the controller. Suggested-by: Sudheesh Mavila <sudheesh.mavila@amd.com> Co-developed-by: Krishnamoorthi M <krishnamoorthi.m@amd.com> Signed-off-by: Krishnamoorthi M <krishnamoorthi.m@amd.com> Co-developed-by: Akshata MukundShetty <akshata.mukundshetty@amd.com> Signed-off-by: Akshata MukundShetty <akshata.mukundshetty@amd.com> Signed-off-by: Raju Rangoju <Raju.Rangoju@amd.com> Link: https://msgid.link/r/20240229134544.3461757-1-Raju.Rangoju@amd.com Signed-off-by: Mark Brown <broonie@kernel.org>
2024-02-29 19:15:44 +05:30
spi: spi_amd: Optimize IO operations Read and write the maximum number of data bytes at once, rather than byte by byte. This improves AMD SPI controller driver performance by reducing the time required to access FIFO registers. For example, with the new changes, 64 bytes of data from the FIFO queue can be read in 8 read calls (8 bytes per call) instead of 64 read calls(1 byte per call). Co-developed-by: Krishnamoorthi M <krishnamoorthi.m@amd.com> Signed-off-by: Krishnamoorthi M <krishnamoorthi.m@amd.com> Co-developed-by: Akshata MukundShetty <akshata.mukundshetty@amd.com> Signed-off-by: Akshata MukundShetty <akshata.mukundshetty@amd.com> Signed-off-by: Raju Rangoju <Raju.Rangoju@amd.com> Link: https://patch.msgid.link/20240925133644.2922359-6-Raju.Rangoju@amd.com Signed-off-by: Mark Brown <broonie@kernel.org>
2024-09-25 19:06:41 +05:30
spi: spi_amd: Add support for SPI MEM framework Add support to the SPI controller driver to use SPI MEM framework. SPI subsystem utilizing the SPI memory operations allows to re-use SPI controller drivers for both SPI NOR devices, regular SPI devices as well as SPI NAND devices. Add below functions of spi_mem_ops to support SPI MEM framework - exec-op(): to execute the memory operations. - supports_op(): to check if the memory operation is supported. - adjust_op_size(): to split data transfers so that they don’t exceed the max transfer size supported by the controller. Suggested-by: Sudheesh Mavila <sudheesh.mavila@amd.com> Co-developed-by: Krishnamoorthi M <krishnamoorthi.m@amd.com> Signed-off-by: Krishnamoorthi M <krishnamoorthi.m@amd.com> Co-developed-by: Akshata MukundShetty <akshata.mukundshetty@amd.com> Signed-off-by: Akshata MukundShetty <akshata.mukundshetty@amd.com> Signed-off-by: Raju Rangoju <Raju.Rangoju@amd.com> Link: https://msgid.link/r/20240229134544.3461757-1-Raju.Rangoju@amd.com Signed-off-by: Mark Brown <broonie@kernel.org>
2024-02-29 19:15:44 +05:30
spi: spi_amd: Optimize IO operations Read and write the maximum number of data bytes at once, rather than byte by byte. This improves AMD SPI controller driver performance by reducing the time required to access FIFO registers. For example, with the new changes, 64 bytes of data from the FIFO queue can be read in 8 read calls (8 bytes per call) instead of 64 read calls(1 byte per call). Co-developed-by: Krishnamoorthi M <krishnamoorthi.m@amd.com> Signed-off-by: Krishnamoorthi M <krishnamoorthi.m@amd.com> Co-developed-by: Akshata MukundShetty <akshata.mukundshetty@amd.com> Signed-off-by: Akshata MukundShetty <akshata.mukundshetty@amd.com> Signed-off-by: Raju Rangoju <Raju.Rangoju@amd.com> Link: https://patch.msgid.link/20240925133644.2922359-6-Raju.Rangoju@amd.com Signed-off-by: Mark Brown <broonie@kernel.org>
2024-09-25 19:06:41 +05:30
spi: spi_amd: Add HIDDMA basic read support SPI index mode has hardware limitation of reading only 64 bytes per transaction due to fixed number of FIFO registers. This constraint leads to performance issues when reading data from NAND/NOR flash devices, as the controller must issue multiple requests to read 64-byte chunks, even if the slave can send up to 2 or 4 KB in single transaction. The AMD HID2 SPI controller supports DMA mode, which allows reading up to 4 KB of data in single transaction. This patch introduces changes to implement HID2 DMA read support for the HID2 SPI controller. Co-developed-by: Krishnamoorthi M <krishnamoorthi.m@amd.com> Signed-off-by: Krishnamoorthi M <krishnamoorthi.m@amd.com> Co-developed-by: Akshata MukundShetty <akshata.mukundshetty@amd.com> Signed-off-by: Akshata MukundShetty <akshata.mukundshetty@amd.com> Signed-off-by: Raju Rangoju <Raju.Rangoju@amd.com> Link: https://patch.msgid.link/20240925133644.2922359-9-Raju.Rangoju@amd.com Signed-off-by: Mark Brown <broonie@kernel.org>
2024-09-25 19:06:44 +05:30
spi: spi_amd: Optimize IO operations Read and write the maximum number of data bytes at once, rather than byte by byte. This improves AMD SPI controller driver performance by reducing the time required to access FIFO registers. For example, with the new changes, 64 bytes of data from the FIFO queue can be read in 8 read calls (8 bytes per call) instead of 64 read calls(1 byte per call). Co-developed-by: Krishnamoorthi M <krishnamoorthi.m@amd.com> Signed-off-by: Krishnamoorthi M <krishnamoorthi.m@amd.com> Co-developed-by: Akshata MukundShetty <akshata.mukundshetty@amd.com> Signed-off-by: Akshata MukundShetty <akshata.mukundshetty@amd.com> Signed-off-by: Raju Rangoju <Raju.Rangoju@amd.com> Link: https://patch.msgid.link/20240925133644.2922359-6-Raju.Rangoju@amd.com Signed-off-by: Mark Brown <broonie@kernel.org>
2024-09-25 19:06:41 +05:30
spi: spi_amd: Add support for SPI MEM framework Add support to the SPI controller driver to use SPI MEM framework. SPI subsystem utilizing the SPI memory operations allows to re-use SPI controller drivers for both SPI NOR devices, regular SPI devices as well as SPI NAND devices. Add below functions of spi_mem_ops to support SPI MEM framework - exec-op(): to execute the memory operations. - supports_op(): to check if the memory operation is supported. - adjust_op_size(): to split data transfers so that they don’t exceed the max transfer size supported by the controller. Suggested-by: Sudheesh Mavila <sudheesh.mavila@amd.com> Co-developed-by: Krishnamoorthi M <krishnamoorthi.m@amd.com> Signed-off-by: Krishnamoorthi M <krishnamoorthi.m@amd.com> Co-developed-by: Akshata MukundShetty <akshata.mukundshetty@amd.com> Signed-off-by: Akshata MukundShetty <akshata.mukundshetty@amd.com> Signed-off-by: Raju Rangoju <Raju.Rangoju@amd.com> Link: https://msgid.link/r/20240229134544.3461757-1-Raju.Rangoju@amd.com Signed-off-by: Mark Brown <broonie@kernel.org>
2024-02-29 19:15:44 +05:30
spi: spi_amd: Add HIDDMA basic read support SPI index mode has hardware limitation of reading only 64 bytes per transaction due to fixed number of FIFO registers. This constraint leads to performance issues when reading data from NAND/NOR flash devices, as the controller must issue multiple requests to read 64-byte chunks, even if the slave can send up to 2 or 4 KB in single transaction. The AMD HID2 SPI controller supports DMA mode, which allows reading up to 4 KB of data in single transaction. This patch introduces changes to implement HID2 DMA read support for the HID2 SPI controller. Co-developed-by: Krishnamoorthi M <krishnamoorthi.m@amd.com> Signed-off-by: Krishnamoorthi M <krishnamoorthi.m@amd.com> Co-developed-by: Akshata MukundShetty <akshata.mukundshetty@amd.com> Signed-off-by: Akshata MukundShetty <akshata.mukundshetty@amd.com> Signed-off-by: Raju Rangoju <Raju.Rangoju@amd.com> Link: https://patch.msgid.link/20240925133644.2922359-9-Raju.Rangoju@amd.com Signed-off-by: Mark Brown <broonie@kernel.org>
2024-09-25 19:06:44 +05:30
spi: spi_amd: Remove read{q,b} usage on DMA buffer Add changes to replace the usage of read{q,b} MMIO accessors with direct memory copy logic for reading data from DMA buffer. Co-developed-by: Krishnamoorthi M <krishnamoorthi.m@amd.com> Signed-off-by: Krishnamoorthi M <krishnamoorthi.m@amd.com> Signed-off-by: Raju Rangoju <Raju.Rangoju@amd.com> Link: https://patch.msgid.link/20250516100658.585654-2-Raju.Rangoju@amd.com Signed-off-by: Mark Brown <broonie@kernel.org>
2025-05-16 15:36:56 +05:30
spi: spi_amd: Add HIDDMA basic read support SPI index mode has hardware limitation of reading only 64 bytes per transaction due to fixed number of FIFO registers. This constraint leads to performance issues when reading data from NAND/NOR flash devices, as the controller must issue multiple requests to read 64-byte chunks, even if the slave can send up to 2 or 4 KB in single transaction. The AMD HID2 SPI controller supports DMA mode, which allows reading up to 4 KB of data in single transaction. This patch introduces changes to implement HID2 DMA read support for the HID2 SPI controller. Co-developed-by: Krishnamoorthi M <krishnamoorthi.m@amd.com> Signed-off-by: Krishnamoorthi M <krishnamoorthi.m@amd.com> Co-developed-by: Akshata MukundShetty <akshata.mukundshetty@amd.com> Signed-off-by: Akshata MukundShetty <akshata.mukundshetty@amd.com> Signed-off-by: Raju Rangoju <Raju.Rangoju@amd.com> Link: https://patch.msgid.link/20240925133644.2922359-9-Raju.Rangoju@amd.com Signed-off-by: Mark Brown <broonie@kernel.org>
2024-09-25 19:06:44 +05:30
spi: spi_amd: Optimize IO operations Read and write the maximum number of data bytes at once, rather than byte by byte. This improves AMD SPI controller driver performance by reducing the time required to access FIFO registers. For example, with the new changes, 64 bytes of data from the FIFO queue can be read in 8 read calls (8 bytes per call) instead of 64 read calls(1 byte per call). Co-developed-by: Krishnamoorthi M <krishnamoorthi.m@amd.com> Signed-off-by: Krishnamoorthi M <krishnamoorthi.m@amd.com> Co-developed-by: Akshata MukundShetty <akshata.mukundshetty@amd.com> Signed-off-by: Akshata MukundShetty <akshata.mukundshetty@amd.com> Signed-off-by: Raju Rangoju <Raju.Rangoju@amd.com> Link: https://patch.msgid.link/20240925133644.2922359-6-Raju.Rangoju@amd.com Signed-off-by: Mark Brown <broonie@kernel.org>
2024-09-25 19:06:41 +05:30
spi: spi_amd: Remove read{q,b} usage on DMA buffer Add changes to replace the usage of read{q,b} MMIO accessors with direct memory copy logic for reading data from DMA buffer. Co-developed-by: Krishnamoorthi M <krishnamoorthi.m@amd.com> Signed-off-by: Krishnamoorthi M <krishnamoorthi.m@amd.com> Signed-off-by: Raju Rangoju <Raju.Rangoju@amd.com> Link: https://patch.msgid.link/20250516100658.585654-2-Raju.Rangoju@amd.com Signed-off-by: Mark Brown <broonie@kernel.org>
2025-05-16 15:36:56 +05:30
spi: spi_amd: Optimize IO operations Read and write the maximum number of data bytes at once, rather than byte by byte. This improves AMD SPI controller driver performance by reducing the time required to access FIFO registers. For example, with the new changes, 64 bytes of data from the FIFO queue can be read in 8 read calls (8 bytes per call) instead of 64 read calls(1 byte per call). Co-developed-by: Krishnamoorthi M <krishnamoorthi.m@amd.com> Signed-off-by: Krishnamoorthi M <krishnamoorthi.m@amd.com> Co-developed-by: Akshata MukundShetty <akshata.mukundshetty@amd.com> Signed-off-by: Akshata MukundShetty <akshata.mukundshetty@amd.com> Signed-off-by: Raju Rangoju <Raju.Rangoju@amd.com> Link: https://patch.msgid.link/20240925133644.2922359-6-Raju.Rangoju@amd.com Signed-off-by: Mark Brown <broonie@kernel.org>
2024-09-25 19:06:41 +05:30
spi: spi_amd: Add HIDDMA basic read support SPI index mode has hardware limitation of reading only 64 bytes per transaction due to fixed number of FIFO registers. This constraint leads to performance issues when reading data from NAND/NOR flash devices, as the controller must issue multiple requests to read 64-byte chunks, even if the slave can send up to 2 or 4 KB in single transaction. The AMD HID2 SPI controller supports DMA mode, which allows reading up to 4 KB of data in single transaction. This patch introduces changes to implement HID2 DMA read support for the HID2 SPI controller. Co-developed-by: Krishnamoorthi M <krishnamoorthi.m@amd.com> Signed-off-by: Krishnamoorthi M <krishnamoorthi.m@amd.com> Co-developed-by: Akshata MukundShetty <akshata.mukundshetty@amd.com> Signed-off-by: Akshata MukundShetty <akshata.mukundshetty@amd.com> Signed-off-by: Raju Rangoju <Raju.Rangoju@amd.com> Link: https://patch.msgid.link/20240925133644.2922359-9-Raju.Rangoju@amd.com Signed-off-by: Mark Brown <broonie@kernel.org>
2024-09-25 19:06:44 +05:30
spi: spi_amd: Remove read{q,b} usage on DMA buffer Add changes to replace the usage of read{q,b} MMIO accessors with direct memory copy logic for reading data from DMA buffer. Co-developed-by: Krishnamoorthi M <krishnamoorthi.m@amd.com> Signed-off-by: Krishnamoorthi M <krishnamoorthi.m@amd.com> Signed-off-by: Raju Rangoju <Raju.Rangoju@amd.com> Link: https://patch.msgid.link/20250516100658.585654-2-Raju.Rangoju@amd.com Signed-off-by: Mark Brown <broonie@kernel.org>
2025-05-16 15:36:56 +05:30
spi: spi_amd: Add support for SPI MEM framework Add support to the SPI controller driver to use SPI MEM framework. SPI subsystem utilizing the SPI memory operations allows to re-use SPI controller drivers for both SPI NOR devices, regular SPI devices as well as SPI NAND devices. Add below functions of spi_mem_ops to support SPI MEM framework - exec-op(): to execute the memory operations. - supports_op(): to check if the memory operation is supported. - adjust_op_size(): to split data transfers so that they don’t exceed the max transfer size supported by the controller. Suggested-by: Sudheesh Mavila <sudheesh.mavila@amd.com> Co-developed-by: Krishnamoorthi M <krishnamoorthi.m@amd.com> Signed-off-by: Krishnamoorthi M <krishnamoorthi.m@amd.com> Co-developed-by: Akshata MukundShetty <akshata.mukundshetty@amd.com> Signed-off-by: Akshata MukundShetty <akshata.mukundshetty@amd.com> Signed-off-by: Raju Rangoju <Raju.Rangoju@amd.com> Link: https://msgid.link/r/20240229134544.3461757-1-Raju.Rangoju@amd.com Signed-off-by: Mark Brown <broonie@kernel.org>
2024-02-29 19:15:44 +05:30
spi: spi_amd: Add HIDDMA basic read support SPI index mode has hardware limitation of reading only 64 bytes per transaction due to fixed number of FIFO registers. This constraint leads to performance issues when reading data from NAND/NOR flash devices, as the controller must issue multiple requests to read 64-byte chunks, even if the slave can send up to 2 or 4 KB in single transaction. The AMD HID2 SPI controller supports DMA mode, which allows reading up to 4 KB of data in single transaction. This patch introduces changes to implement HID2 DMA read support for the HID2 SPI controller. Co-developed-by: Krishnamoorthi M <krishnamoorthi.m@amd.com> Signed-off-by: Krishnamoorthi M <krishnamoorthi.m@amd.com> Co-developed-by: Akshata MukundShetty <akshata.mukundshetty@amd.com> Signed-off-by: Akshata MukundShetty <akshata.mukundshetty@amd.com> Signed-off-by: Raju Rangoju <Raju.Rangoju@amd.com> Link: https://patch.msgid.link/20240925133644.2922359-9-Raju.Rangoju@amd.com Signed-off-by: Mark Brown <broonie@kernel.org>
2024-09-25 19:06:44 +05:30
spi: spi_amd: Optimize IO operations Read and write the maximum number of data bytes at once, rather than byte by byte. This improves AMD SPI controller driver performance by reducing the time required to access FIFO registers. For example, with the new changes, 64 bytes of data from the FIFO queue can be read in 8 read calls (8 bytes per call) instead of 64 read calls(1 byte per call). Co-developed-by: Krishnamoorthi M <krishnamoorthi.m@amd.com> Signed-off-by: Krishnamoorthi M <krishnamoorthi.m@amd.com> Co-developed-by: Akshata MukundShetty <akshata.mukundshetty@amd.com> Signed-off-by: Akshata MukundShetty <akshata.mukundshetty@amd.com> Signed-off-by: Raju Rangoju <Raju.Rangoju@amd.com> Link: https://patch.msgid.link/20240925133644.2922359-6-Raju.Rangoju@amd.com Signed-off-by: Mark Brown <broonie@kernel.org>
2024-09-25 19:06:41 +05:30
spi: spi_amd: Add support for SPI MEM framework Add support to the SPI controller driver to use SPI MEM framework. SPI subsystem utilizing the SPI memory operations allows to re-use SPI controller drivers for both SPI NOR devices, regular SPI devices as well as SPI NAND devices. Add below functions of spi_mem_ops to support SPI MEM framework - exec-op(): to execute the memory operations. - supports_op(): to check if the memory operation is supported. - adjust_op_size(): to split data transfers so that they don’t exceed the max transfer size supported by the controller. Suggested-by: Sudheesh Mavila <sudheesh.mavila@amd.com> Co-developed-by: Krishnamoorthi M <krishnamoorthi.m@amd.com> Signed-off-by: Krishnamoorthi M <krishnamoorthi.m@amd.com> Co-developed-by: Akshata MukundShetty <akshata.mukundshetty@amd.com> Signed-off-by: Akshata MukundShetty <akshata.mukundshetty@amd.com> Signed-off-by: Raju Rangoju <Raju.Rangoju@amd.com> Link: https://msgid.link/r/20240229134544.3461757-1-Raju.Rangoju@amd.com Signed-off-by: Mark Brown <broonie@kernel.org>
2024-02-29 19:15:44 +05:30
spi: spi_amd: Set controller address mode Add changes to set the controller address mode before initiating commands. The AMD SPI0 controller(AMDI0062) supports both 24-bit and 32-bit address modes, while the HID2 SPI controller(AMDI0063) supports only the 24-bit address mode. So this change is applicable only for SPI0 controller. Co-developed-by: Krishnamoorthi M <krishnamoorthi.m@amd.com> Signed-off-by: Krishnamoorthi M <krishnamoorthi.m@amd.com> Co-developed-by: Akshata MukundShetty <akshata.mukundshetty@amd.com> Signed-off-by: Akshata MukundShetty <akshata.mukundshetty@amd.com> Signed-off-by: Raju Rangoju <Raju.Rangoju@amd.com> Link: https://patch.msgid.link/20240925133644.2922359-8-Raju.Rangoju@amd.com Signed-off-by: Mark Brown <broonie@kernel.org>
2024-09-25 19:06:43 +05:30
spi: spi_amd: Add support for SPI MEM framework Add support to the SPI controller driver to use SPI MEM framework. SPI subsystem utilizing the SPI memory operations allows to re-use SPI controller drivers for both SPI NOR devices, regular SPI devices as well as SPI NAND devices. Add below functions of spi_mem_ops to support SPI MEM framework - exec-op(): to execute the memory operations. - supports_op(): to check if the memory operation is supported. - adjust_op_size(): to split data transfers so that they don’t exceed the max transfer size supported by the controller. Suggested-by: Sudheesh Mavila <sudheesh.mavila@amd.com> Co-developed-by: Krishnamoorthi M <krishnamoorthi.m@amd.com> Signed-off-by: Krishnamoorthi M <krishnamoorthi.m@amd.com> Co-developed-by: Akshata MukundShetty <akshata.mukundshetty@amd.com> Signed-off-by: Akshata MukundShetty <akshata.mukundshetty@amd.com> Signed-off-by: Raju Rangoju <Raju.Rangoju@amd.com> Link: https://msgid.link/r/20240229134544.3461757-1-Raju.Rangoju@amd.com Signed-off-by: Mark Brown <broonie@kernel.org>
2024-02-29 19:15:44 +05:30
spi: amd: Drop redundant check Both spi and spi-mem cores already take care of checking the minimum and maximum speed for transfers depending on the controller capabilities. There is no reason to repeat this check in controller drivers. Once this possible error condition removed from the function, it makes no longer sense to return an int. Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> Link: https://patch.msgid.link/20241224-winbond-6-11-rc1-quad-support-v2-4-ad218dbc406f@bootlin.com Signed-off-by: Mark Brown <broonie@kernel.org>
2024-12-24 18:05:49 +01:00
spi: spi_amd: Add support for SPI MEM framework Add support to the SPI controller driver to use SPI MEM framework. SPI subsystem utilizing the SPI memory operations allows to re-use SPI controller drivers for both SPI NOR devices, regular SPI devices as well as SPI NAND devices. Add below functions of spi_mem_ops to support SPI MEM framework - exec-op(): to execute the memory operations. - supports_op(): to check if the memory operation is supported. - adjust_op_size(): to split data transfers so that they don’t exceed the max transfer size supported by the controller. Suggested-by: Sudheesh Mavila <sudheesh.mavila@amd.com> Co-developed-by: Krishnamoorthi M <krishnamoorthi.m@amd.com> Signed-off-by: Krishnamoorthi M <krishnamoorthi.m@amd.com> Co-developed-by: Akshata MukundShetty <akshata.mukundshetty@amd.com> Signed-off-by: Akshata MukundShetty <akshata.mukundshetty@amd.com> Signed-off-by: Raju Rangoju <Raju.Rangoju@amd.com> Link: https://msgid.link/r/20240229134544.3461757-1-Raju.Rangoju@amd.com Signed-off-by: Mark Brown <broonie@kernel.org>
2024-02-29 19:15:44 +05:30
spi: spi_amd: Set controller address mode Add changes to set the controller address mode before initiating commands. The AMD SPI0 controller(AMDI0062) supports both 24-bit and 32-bit address modes, while the HID2 SPI controller(AMDI0063) supports only the 24-bit address mode. So this change is applicable only for SPI0 controller. Co-developed-by: Krishnamoorthi M <krishnamoorthi.m@amd.com> Signed-off-by: Krishnamoorthi M <krishnamoorthi.m@amd.com> Co-developed-by: Akshata MukundShetty <akshata.mukundshetty@amd.com> Signed-off-by: Akshata MukundShetty <akshata.mukundshetty@amd.com> Signed-off-by: Raju Rangoju <Raju.Rangoju@amd.com> Link: https://patch.msgid.link/20240925133644.2922359-8-Raju.Rangoju@amd.com Signed-off-by: Mark Brown <broonie@kernel.org>
2024-09-25 19:06:43 +05:30
spi: spi_amd: Add support for SPI MEM framework Add support to the SPI controller driver to use SPI MEM framework. SPI subsystem utilizing the SPI memory operations allows to re-use SPI controller drivers for both SPI NOR devices, regular SPI devices as well as SPI NAND devices. Add below functions of spi_mem_ops to support SPI MEM framework - exec-op(): to execute the memory operations. - supports_op(): to check if the memory operation is supported. - adjust_op_size(): to split data transfers so that they don’t exceed the max transfer size supported by the controller. Suggested-by: Sudheesh Mavila <sudheesh.mavila@amd.com> Co-developed-by: Krishnamoorthi M <krishnamoorthi.m@amd.com> Signed-off-by: Krishnamoorthi M <krishnamoorthi.m@amd.com> Co-developed-by: Akshata MukundShetty <akshata.mukundshetty@amd.com> Signed-off-by: Akshata MukundShetty <akshata.mukundshetty@amd.com> Signed-off-by: Raju Rangoju <Raju.Rangoju@amd.com> Link: https://msgid.link/r/20240229134544.3461757-1-Raju.Rangoju@amd.com Signed-off-by: Mark Brown <broonie@kernel.org>
2024-02-29 19:15:44 +05:30
spi: amd: Fix -Wuninitialized in amd_spi_exec_mem_op() After commit e6204f39fe3a ("spi: amd: Drop redundant check"), clang warns (or errors with CONFIG_WERROR=y): drivers/spi/spi-amd.c:695:9: error: variable 'ret' is uninitialized when used here [-Werror,-Wuninitialized] 695 | return ret; | ^~~ drivers/spi/spi-amd.c:673:9: note: initialize the variable 'ret' to silence this warning 673 | int ret; | ^ | = 0 1 error generated. ret is no longer set on anything other than the default switch path. Replace ret with a direct return of 0 at the end of the function and -EOPNOTSUPP in the default case to resolve the warning. Fixes: e6204f39fe3a ("spi: amd: Drop redundant check") Reported-by: kernel test robot <lkp@intel.com> Closes: https://lore.kernel.org/oe-kbuild-all/202501112315.ugYQ7Ce7-lkp@intel.com/ Signed-off-by: Nathan Chancellor <nathan@kernel.org> Reviewed-by: Miguel Ojeda <ojeda@kernel.org> Reviewed-by: Miquel Raynal <miquel.raynal@bootlin.com> Link: https://patch.msgid.link/20250111-spi-amd-fix-uninitialized-ret-v1-1-c66ab9f6a23d@kernel.org Signed-off-by: Mark Brown <broonie@kernel.org>
2025-01-11 12:08:38 -07:00
spi: spi_amd: Add support for SPI MEM framework Add support to the SPI controller driver to use SPI MEM framework. SPI subsystem utilizing the SPI memory operations allows to re-use SPI controller drivers for both SPI NOR devices, regular SPI devices as well as SPI NAND devices. Add below functions of spi_mem_ops to support SPI MEM framework - exec-op(): to execute the memory operations. - supports_op(): to check if the memory operation is supported. - adjust_op_size(): to split data transfers so that they don’t exceed the max transfer size supported by the controller. Suggested-by: Sudheesh Mavila <sudheesh.mavila@amd.com> Co-developed-by: Krishnamoorthi M <krishnamoorthi.m@amd.com> Signed-off-by: Krishnamoorthi M <krishnamoorthi.m@amd.com> Co-developed-by: Akshata MukundShetty <akshata.mukundshetty@amd.com> Signed-off-by: Akshata MukundShetty <akshata.mukundshetty@amd.com> Signed-off-by: Raju Rangoju <Raju.Rangoju@amd.com> Link: https://msgid.link/r/20240229134544.3461757-1-Raju.Rangoju@amd.com Signed-off-by: Mark Brown <broonie@kernel.org>
2024-02-29 19:15:44 +05:30
spi: amd: Fix -Wuninitialized in amd_spi_exec_mem_op() After commit e6204f39fe3a ("spi: amd: Drop redundant check"), clang warns (or errors with CONFIG_WERROR=y): drivers/spi/spi-amd.c:695:9: error: variable 'ret' is uninitialized when used here [-Werror,-Wuninitialized] 695 | return ret; | ^~~ drivers/spi/spi-amd.c:673:9: note: initialize the variable 'ret' to silence this warning 673 | int ret; | ^ | = 0 1 error generated. ret is no longer set on anything other than the default switch path. Replace ret with a direct return of 0 at the end of the function and -EOPNOTSUPP in the default case to resolve the warning. Fixes: e6204f39fe3a ("spi: amd: Drop redundant check") Reported-by: kernel test robot <lkp@intel.com> Closes: https://lore.kernel.org/oe-kbuild-all/202501112315.ugYQ7Ce7-lkp@intel.com/ Signed-off-by: Nathan Chancellor <nathan@kernel.org> Reviewed-by: Miguel Ojeda <ojeda@kernel.org> Reviewed-by: Miquel Raynal <miquel.raynal@bootlin.com> Link: https://patch.msgid.link/20250111-spi-amd-fix-uninitialized-ret-v1-1-c66ab9f6a23d@kernel.org Signed-off-by: Mark Brown <broonie@kernel.org>
2025-01-11 12:08:38 -07:00
spi: spi_amd: Add support for SPI MEM framework Add support to the SPI controller driver to use SPI MEM framework. SPI subsystem utilizing the SPI memory operations allows to re-use SPI controller drivers for both SPI NOR devices, regular SPI devices as well as SPI NAND devices. Add below functions of spi_mem_ops to support SPI MEM framework - exec-op(): to execute the memory operations. - supports_op(): to check if the memory operation is supported. - adjust_op_size(): to split data transfers so that they don’t exceed the max transfer size supported by the controller. Suggested-by: Sudheesh Mavila <sudheesh.mavila@amd.com> Co-developed-by: Krishnamoorthi M <krishnamoorthi.m@amd.com> Signed-off-by: Krishnamoorthi M <krishnamoorthi.m@amd.com> Co-developed-by: Akshata MukundShetty <akshata.mukundshetty@amd.com> Signed-off-by: Akshata MukundShetty <akshata.mukundshetty@amd.com> Signed-off-by: Raju Rangoju <Raju.Rangoju@amd.com> Link: https://msgid.link/r/20240229134544.3461757-1-Raju.Rangoju@amd.com Signed-off-by: Mark Brown <broonie@kernel.org>
2024-02-29 19:15:44 +05:30
spi: amd: Support per spi-mem operation frequency switches Every ->exec_op() call correctly configures the spi bus speed to the maximum allowed frequency for the memory using the constant spi default parameter. Since we can now have per-operation constraints, let's use the value that comes from the spi-mem operation structure instead. In case there is no specific limitation for this operation, the default spi device value will be given anyway. This controller however performed a frequency check, which is also observed during the ->check_op() phase. The per-operation frequency capability is thus advertised to the spi-mem core. Cc: Sanjay R Mehta <sanju.mehta@amd.com> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> Link: https://patch.msgid.link/20241224-winbond-6-11-rc1-quad-support-v2-3-ad218dbc406f@bootlin.com Signed-off-by: Mark Brown <broonie@kernel.org>
2024-12-24 18:05:48 +01:00
spi: amd: switch to use modern name Change legacy name master to modern name host or controller. No functional changed. Signed-off-by: Yang Yingliang <yangyingliang@huawei.com> Link: https://lore.kernel.org/r/20230728093221.3312026-2-yangyingliang@huawei.com Signed-off-by: Mark Brown <broonie@kernel.org>
2023-07-28 17:32:01 +08:00
spi: spi-amd: Add AMD SPI controller driver support This driver supports SPI Controller for AMD SOCs.This driver supports SPI operations using FIFO mode of transfer. Signed-off-by: Sanjay R Mehta <sanju.mehta@amd.com> Signed-off-by: Mark Brown <broonie@kernel.org> Link: https://lore.kernel.org/r/1587844788-33997-1-git-send-email-sanju.mehta@amd.com Signed-off-by: Mark Brown <broonie@kernel.org>
2020-04-25 14:59:48 -05:00
spi: amd: switch to use modern name Change legacy name master to modern name host or controller. No functional changed. Signed-off-by: Yang Yingliang <yangyingliang@huawei.com> Link: https://lore.kernel.org/r/20230728093221.3312026-2-yangyingliang@huawei.com Signed-off-by: Mark Brown <broonie@kernel.org>
2023-07-28 17:32:01 +08:00
spi: spi-amd: Add AMD SPI controller driver support This driver supports SPI Controller for AMD SOCs.This driver supports SPI operations using FIFO mode of transfer. Signed-off-by: Sanjay R Mehta <sanju.mehta@amd.com> Signed-off-by: Mark Brown <broonie@kernel.org> Link: https://lore.kernel.org/r/1587844788-33997-1-git-send-email-sanju.mehta@amd.com Signed-off-by: Mark Brown <broonie@kernel.org>
2020-04-25 14:59:48 -05:00
spi: Replace all spi->chip_select and spi->cs_gpiod references with function call Supporting multi-cs in spi drivers would require the chip_select & cs_gpiod members of struct spi_device to be an array. But changing the type of these members to array would break the spi driver functionality. To make the transition smoother introduced four new APIs to get/set the spi->chip_select & spi->cs_gpiod and replaced all spi->chip_select and spi->cs_gpiod references with get or set API calls. While adding multi-cs support in further patches the chip_select & cs_gpiod members of the spi_device structure would be converted to arrays & the "idx" parameter of the APIs would be used as array index i.e., spi->chip_select[idx] & spi->cs_gpiod[idx] respectively. Signed-off-by: Amit Kumar Mahapatra <amit.kumar-mahapatra@amd.com> Acked-by: Heiko Stuebner <heiko@sntech.de> # Rockchip drivers Reviewed-by: Michal Simek <michal.simek@amd.com> Reviewed-by: Cédric Le Goater <clg@kaod.org> # Aspeed driver Reviewed-by: Dhruva Gole <d-gole@ti.com> # SPI Cadence QSPI Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com> # spi-stm32-qspi Acked-by: William Zhang <william.zhang@broadcom.com> # bcm63xx-hsspi driver Reviewed-by: Serge Semin <fancer.lancer@gmail.com> # DW SSI part Link: https://lore.kernel.org/r/167847070432.26.15076794204368669839@mailman-core.alsa-project.org Signed-off-by: Mark Brown <broonie@kernel.org>
2023-03-10 23:02:03 +05:30
spi: spi-amd: Add AMD SPI controller driver support This driver supports SPI Controller for AMD SOCs.This driver supports SPI operations using FIFO mode of transfer. Signed-off-by: Sanjay R Mehta <sanju.mehta@amd.com> Signed-off-by: Mark Brown <broonie@kernel.org> Link: https://lore.kernel.org/r/1587844788-33997-1-git-send-email-sanju.mehta@amd.com Signed-off-by: Mark Brown <broonie@kernel.org>
2020-04-25 14:59:48 -05:00
spi: amd: switch to use modern name Change legacy name master to modern name host or controller. No functional changed. Signed-off-by: Yang Yingliang <yangyingliang@huawei.com> Link: https://lore.kernel.org/r/20230728093221.3312026-2-yangyingliang@huawei.com Signed-off-by: Mark Brown <broonie@kernel.org>
2023-07-28 17:32:01 +08:00
spi: spi-amd: Add AMD SPI controller driver support This driver supports SPI Controller for AMD SOCs.This driver supports SPI operations using FIFO mode of transfer. Signed-off-by: Sanjay R Mehta <sanju.mehta@amd.com> Signed-off-by: Mark Brown <broonie@kernel.org> Link: https://lore.kernel.org/r/1587844788-33997-1-git-send-email-sanju.mehta@amd.com Signed-off-by: Mark Brown <broonie@kernel.org>
2020-04-25 14:59:48 -05:00
spi: amd: Limit max transfer and message size Enabling the SPI CS35L41 audio codec driver for Steam Deck [1] revealed a problem with the current AMD SPI controller driver implementation, consisting of an unrecoverable system hang. The issue can be prevented if we ensure the max transfer size and the max message size do not exceed the FIFO buffer size. According to the implementation of the downstream driver, the AMD SPI controller is not able to handle more than 70 bytes per transfer, which corresponds to the size of the FIFO buffer. Hence, let's fix this by setting the SPI limits mentioned above. [1] https://lore.kernel.org/r/20220621213819.262537-1-cristian.ciocaltea@collabora.com Reported-by: Anastasios Vacharakis <vacharakis@o2mail.de> Fixes: bbb336f39efc ("spi: spi-amd: Add AMD SPI controller driver support") Signed-off-by: Cristian Ciocaltea <cristian.ciocaltea@collabora.com> Link: https://lore.kernel.org/r/20220706100626.1234731-2-cristian.ciocaltea@collabora.com Signed-off-by: Mark Brown <broonie@kernel.org>
2022-07-06 13:06:22 +03:00
spi: spi_amd: Add HIDDMA basic read support SPI index mode has hardware limitation of reading only 64 bytes per transaction due to fixed number of FIFO registers. This constraint leads to performance issues when reading data from NAND/NOR flash devices, as the controller must issue multiple requests to read 64-byte chunks, even if the slave can send up to 2 or 4 KB in single transaction. The AMD HID2 SPI controller supports DMA mode, which allows reading up to 4 KB of data in single transaction. This patch introduces changes to implement HID2 DMA read support for the HID2 SPI controller. Co-developed-by: Krishnamoorthi M <krishnamoorthi.m@amd.com> Signed-off-by: Krishnamoorthi M <krishnamoorthi.m@amd.com> Co-developed-by: Akshata MukundShetty <akshata.mukundshetty@amd.com> Signed-off-by: Akshata MukundShetty <akshata.mukundshetty@amd.com> Signed-off-by: Raju Rangoju <Raju.Rangoju@amd.com> Link: https://patch.msgid.link/20240925133644.2922359-9-Raju.Rangoju@amd.com Signed-off-by: Mark Brown <broonie@kernel.org>
2024-09-25 19:06:44 +05:30
spi: spi_amd: Add HIDDMA basic write support SPI index mode has hardware limitation of transferring only 64 bytes per transaction due to fixed number of FIFO registers. This constraint leads to performance issues when reading/writing data to/from NAND/NOR flash devices, as the controller must issue multiple requests to read/write 64-byte chunks, even if the slave can transfer up to 2 or 4 KB in a single transaction. The AMD HID2 SPI controller supports DMA mode, allowing for reading/writing up to 4 KB of data in a single transaction. The existing spi_amd driver already supports HID2 DMA read operations. This patch introduces changes to implement HID2 DMA single mode basic write support for the HID2 SPI controller. Co-developed-by: Krishnamoorthi M <krishnamoorthi.m@amd.com> Signed-off-by: Krishnamoorthi M <krishnamoorthi.m@amd.com> Co-developed-by: Akshata MukundShetty <akshata.mukundshetty@amd.com> Signed-off-by: Akshata MukundShetty <akshata.mukundshetty@amd.com> Signed-off-by: Raju Rangoju <Raju.Rangoju@amd.com> Link: https://patch.msgid.link/20250516100658.585654-3-Raju.Rangoju@amd.com Signed-off-by: Mark Brown <broonie@kernel.org>
2025-05-16 15:36:57 +05:30
spi: spi_amd: Add HIDDMA basic read support SPI index mode has hardware limitation of reading only 64 bytes per transaction due to fixed number of FIFO registers. This constraint leads to performance issues when reading data from NAND/NOR flash devices, as the controller must issue multiple requests to read 64-byte chunks, even if the slave can send up to 2 or 4 KB in single transaction. The AMD HID2 SPI controller supports DMA mode, which allows reading up to 4 KB of data in single transaction. This patch introduces changes to implement HID2 DMA read support for the HID2 SPI controller. Co-developed-by: Krishnamoorthi M <krishnamoorthi.m@amd.com> Signed-off-by: Krishnamoorthi M <krishnamoorthi.m@amd.com> Co-developed-by: Akshata MukundShetty <akshata.mukundshetty@amd.com> Signed-off-by: Akshata MukundShetty <akshata.mukundshetty@amd.com> Signed-off-by: Raju Rangoju <Raju.Rangoju@amd.com> Link: https://patch.msgid.link/20240925133644.2922359-9-Raju.Rangoju@amd.com Signed-off-by: Mark Brown <broonie@kernel.org>
2024-09-25 19:06:44 +05:30
spi: spi_amd: Add HIDDMA basic write support SPI index mode has hardware limitation of transferring only 64 bytes per transaction due to fixed number of FIFO registers. This constraint leads to performance issues when reading/writing data to/from NAND/NOR flash devices, as the controller must issue multiple requests to read/write 64-byte chunks, even if the slave can transfer up to 2 or 4 KB in a single transaction. The AMD HID2 SPI controller supports DMA mode, allowing for reading/writing up to 4 KB of data in a single transaction. The existing spi_amd driver already supports HID2 DMA read operations. This patch introduces changes to implement HID2 DMA single mode basic write support for the HID2 SPI controller. Co-developed-by: Krishnamoorthi M <krishnamoorthi.m@amd.com> Signed-off-by: Krishnamoorthi M <krishnamoorthi.m@amd.com> Co-developed-by: Akshata MukundShetty <akshata.mukundshetty@amd.com> Signed-off-by: Akshata MukundShetty <akshata.mukundshetty@amd.com> Signed-off-by: Raju Rangoju <Raju.Rangoju@amd.com> Link: https://patch.msgid.link/20250516100658.585654-3-Raju.Rangoju@amd.com Signed-off-by: Mark Brown <broonie@kernel.org>
2025-05-16 15:36:57 +05:30
spi: spi_amd: Add HIDDMA basic read support SPI index mode has hardware limitation of reading only 64 bytes per transaction due to fixed number of FIFO registers. This constraint leads to performance issues when reading data from NAND/NOR flash devices, as the controller must issue multiple requests to read 64-byte chunks, even if the slave can send up to 2 or 4 KB in single transaction. The AMD HID2 SPI controller supports DMA mode, which allows reading up to 4 KB of data in single transaction. This patch introduces changes to implement HID2 DMA read support for the HID2 SPI controller. Co-developed-by: Krishnamoorthi M <krishnamoorthi.m@amd.com> Signed-off-by: Krishnamoorthi M <krishnamoorthi.m@amd.com> Co-developed-by: Akshata MukundShetty <akshata.mukundshetty@amd.com> Signed-off-by: Akshata MukundShetty <akshata.mukundshetty@amd.com> Signed-off-by: Raju Rangoju <Raju.Rangoju@amd.com> Link: https://patch.msgid.link/20240925133644.2922359-9-Raju.Rangoju@amd.com Signed-off-by: Mark Brown <broonie@kernel.org>
2024-09-25 19:06:44 +05:30
spi: spi_amd: Add HIDDMA basic write support SPI index mode has hardware limitation of transferring only 64 bytes per transaction due to fixed number of FIFO registers. This constraint leads to performance issues when reading/writing data to/from NAND/NOR flash devices, as the controller must issue multiple requests to read/write 64-byte chunks, even if the slave can transfer up to 2 or 4 KB in a single transaction. The AMD HID2 SPI controller supports DMA mode, allowing for reading/writing up to 4 KB of data in a single transaction. The existing spi_amd driver already supports HID2 DMA read operations. This patch introduces changes to implement HID2 DMA single mode basic write support for the HID2 SPI controller. Co-developed-by: Krishnamoorthi M <krishnamoorthi.m@amd.com> Signed-off-by: Krishnamoorthi M <krishnamoorthi.m@amd.com> Co-developed-by: Akshata MukundShetty <akshata.mukundshetty@amd.com> Signed-off-by: Akshata MukundShetty <akshata.mukundshetty@amd.com> Signed-off-by: Raju Rangoju <Raju.Rangoju@amd.com> Link: https://patch.msgid.link/20250516100658.585654-3-Raju.Rangoju@amd.com Signed-off-by: Mark Brown <broonie@kernel.org>
2025-05-16 15:36:57 +05:30
spi: spi_amd: Add HIDDMA basic read support SPI index mode has hardware limitation of reading only 64 bytes per transaction due to fixed number of FIFO registers. This constraint leads to performance issues when reading data from NAND/NOR flash devices, as the controller must issue multiple requests to read 64-byte chunks, even if the slave can send up to 2 or 4 KB in single transaction. The AMD HID2 SPI controller supports DMA mode, which allows reading up to 4 KB of data in single transaction. This patch introduces changes to implement HID2 DMA read support for the HID2 SPI controller. Co-developed-by: Krishnamoorthi M <krishnamoorthi.m@amd.com> Signed-off-by: Krishnamoorthi M <krishnamoorthi.m@amd.com> Co-developed-by: Akshata MukundShetty <akshata.mukundshetty@amd.com> Signed-off-by: Akshata MukundShetty <akshata.mukundshetty@amd.com> Signed-off-by: Raju Rangoju <Raju.Rangoju@amd.com> Link: https://patch.msgid.link/20240925133644.2922359-9-Raju.Rangoju@amd.com Signed-off-by: Mark Brown <broonie@kernel.org>
2024-09-25 19:06:44 +05:30
spi: spi_amd: Add HIDDMA basic write support SPI index mode has hardware limitation of transferring only 64 bytes per transaction due to fixed number of FIFO registers. This constraint leads to performance issues when reading/writing data to/from NAND/NOR flash devices, as the controller must issue multiple requests to read/write 64-byte chunks, even if the slave can transfer up to 2 or 4 KB in a single transaction. The AMD HID2 SPI controller supports DMA mode, allowing for reading/writing up to 4 KB of data in a single transaction. The existing spi_amd driver already supports HID2 DMA read operations. This patch introduces changes to implement HID2 DMA single mode basic write support for the HID2 SPI controller. Co-developed-by: Krishnamoorthi M <krishnamoorthi.m@amd.com> Signed-off-by: Krishnamoorthi M <krishnamoorthi.m@amd.com> Co-developed-by: Akshata MukundShetty <akshata.mukundshetty@amd.com> Signed-off-by: Akshata MukundShetty <akshata.mukundshetty@amd.com> Signed-off-by: Raju Rangoju <Raju.Rangoju@amd.com> Link: https://patch.msgid.link/20250516100658.585654-3-Raju.Rangoju@amd.com Signed-off-by: Mark Brown <broonie@kernel.org>
2025-05-16 15:36:57 +05:30
spi: spi_amd: Add HIDDMA basic read support SPI index mode has hardware limitation of reading only 64 bytes per transaction due to fixed number of FIFO registers. This constraint leads to performance issues when reading data from NAND/NOR flash devices, as the controller must issue multiple requests to read 64-byte chunks, even if the slave can send up to 2 or 4 KB in single transaction. The AMD HID2 SPI controller supports DMA mode, which allows reading up to 4 KB of data in single transaction. This patch introduces changes to implement HID2 DMA read support for the HID2 SPI controller. Co-developed-by: Krishnamoorthi M <krishnamoorthi.m@amd.com> Signed-off-by: Krishnamoorthi M <krishnamoorthi.m@amd.com> Co-developed-by: Akshata MukundShetty <akshata.mukundshetty@amd.com> Signed-off-by: Akshata MukundShetty <akshata.mukundshetty@amd.com> Signed-off-by: Raju Rangoju <Raju.Rangoju@amd.com> Link: https://patch.msgid.link/20240925133644.2922359-9-Raju.Rangoju@amd.com Signed-off-by: Mark Brown <broonie@kernel.org>
2024-09-25 19:06:44 +05:30
spi: spi_amd: Add HIDDMA basic write support SPI index mode has hardware limitation of transferring only 64 bytes per transaction due to fixed number of FIFO registers. This constraint leads to performance issues when reading/writing data to/from NAND/NOR flash devices, as the controller must issue multiple requests to read/write 64-byte chunks, even if the slave can transfer up to 2 or 4 KB in a single transaction. The AMD HID2 SPI controller supports DMA mode, allowing for reading/writing up to 4 KB of data in a single transaction. The existing spi_amd driver already supports HID2 DMA read operations. This patch introduces changes to implement HID2 DMA single mode basic write support for the HID2 SPI controller. Co-developed-by: Krishnamoorthi M <krishnamoorthi.m@amd.com> Signed-off-by: Krishnamoorthi M <krishnamoorthi.m@amd.com> Co-developed-by: Akshata MukundShetty <akshata.mukundshetty@amd.com> Signed-off-by: Akshata MukundShetty <akshata.mukundshetty@amd.com> Signed-off-by: Raju Rangoju <Raju.Rangoju@amd.com> Link: https://patch.msgid.link/20250516100658.585654-3-Raju.Rangoju@amd.com Signed-off-by: Mark Brown <broonie@kernel.org>
2025-05-16 15:36:57 +05:30
spi: spi_amd: Add HIDDMA basic read support SPI index mode has hardware limitation of reading only 64 bytes per transaction due to fixed number of FIFO registers. This constraint leads to performance issues when reading data from NAND/NOR flash devices, as the controller must issue multiple requests to read 64-byte chunks, even if the slave can send up to 2 or 4 KB in single transaction. The AMD HID2 SPI controller supports DMA mode, which allows reading up to 4 KB of data in single transaction. This patch introduces changes to implement HID2 DMA read support for the HID2 SPI controller. Co-developed-by: Krishnamoorthi M <krishnamoorthi.m@amd.com> Signed-off-by: Krishnamoorthi M <krishnamoorthi.m@amd.com> Co-developed-by: Akshata MukundShetty <akshata.mukundshetty@amd.com> Signed-off-by: Akshata MukundShetty <akshata.mukundshetty@amd.com> Signed-off-by: Raju Rangoju <Raju.Rangoju@amd.com> Link: https://patch.msgid.link/20240925133644.2922359-9-Raju.Rangoju@amd.com Signed-off-by: Mark Brown <broonie@kernel.org>
2024-09-25 19:06:44 +05:30
spi: spi_amd: Add PCI-based driver for AMD HID2 SPI controller Register a new driver(spi_amd_pci) for the HID2 SPI controller using the PCI ID of the LPC bridge device. Add a new common probe function in spi_amd driver to encapsulate the code required for registering the controller driver. This function will be utilized by both the existing ACPI driver and the newly introduced PCI-based driver for the HID2 SPI controller. The MMIO register base address of the HID2 SPI controller can be obtained from the PCI LPC bridge registers. By implementing these changes, the DMA buffer will be correctly associated with the LPC bridge device, preventing IO_PAGE_FAULT caused by IOMMU when the LPC bridge attempts DMA operations on addresses owned by the HID2 SPI controller. Co-developed-by: Krishnamoorthi M <krishnamoorthi.m@amd.com> Signed-off-by: Krishnamoorthi M <krishnamoorthi.m@amd.com> Co-developed-by: Akshata MukundShetty <akshata.mukundshetty@amd.com> Signed-off-by: Akshata MukundShetty <akshata.mukundshetty@amd.com> Signed-off-by: Raju Rangoju <Raju.Rangoju@amd.com> Link: https://patch.msgid.link/20250402121514.2941334-1-Raju.Rangoju@amd.com Signed-off-by: Mark Brown <broonie@kernel.org>
2025-04-02 17:45:14 +05:30
spi: spi-amd: Add AMD SPI controller driver support This driver supports SPI Controller for AMD SOCs.This driver supports SPI operations using FIFO mode of transfer. Signed-off-by: Sanjay R Mehta <sanju.mehta@amd.com> Signed-off-by: Mark Brown <broonie@kernel.org> Link: https://lore.kernel.org/r/1587844788-33997-1-git-send-email-sanju.mehta@amd.com Signed-off-by: Mark Brown <broonie@kernel.org>
2020-04-25 14:59:48 -05:00
spi: spi_amd: Add PCI-based driver for AMD HID2 SPI controller Register a new driver(spi_amd_pci) for the HID2 SPI controller using the PCI ID of the LPC bridge device. Add a new common probe function in spi_amd driver to encapsulate the code required for registering the controller driver. This function will be utilized by both the existing ACPI driver and the newly introduced PCI-based driver for the HID2 SPI controller. The MMIO register base address of the HID2 SPI controller can be obtained from the PCI LPC bridge registers. By implementing these changes, the DMA buffer will be correctly associated with the LPC bridge device, preventing IO_PAGE_FAULT caused by IOMMU when the LPC bridge attempts DMA operations on addresses owned by the HID2 SPI controller. Co-developed-by: Krishnamoorthi M <krishnamoorthi.m@amd.com> Signed-off-by: Krishnamoorthi M <krishnamoorthi.m@amd.com> Co-developed-by: Akshata MukundShetty <akshata.mukundshetty@amd.com> Signed-off-by: Akshata MukundShetty <akshata.mukundshetty@amd.com> Signed-off-by: Raju Rangoju <Raju.Rangoju@amd.com> Link: https://patch.msgid.link/20250402121514.2941334-1-Raju.Rangoju@amd.com Signed-off-by: Mark Brown <broonie@kernel.org>
2025-04-02 17:45:14 +05:30
spi: amd: Make use of devm_spi_alloc_master() Make use of the devm variant of spi_alloc_master() in order to cleanup and simplify the error handling in the probe function by getting rid of the goto statements. Signed-off-by: Cristian Ciocaltea <cristian.ciocaltea@collabora.com> Link: https://lore.kernel.org/r/20220706100626.1234731-3-cristian.ciocaltea@collabora.com Signed-off-by: Mark Brown <broonie@kernel.org>
2022-07-06 13:06:23 +03:00
spi: spi-amd: Add AMD SPI controller driver support This driver supports SPI Controller for AMD SOCs.This driver supports SPI operations using FIFO mode of transfer. Signed-off-by: Sanjay R Mehta <sanju.mehta@amd.com> Signed-off-by: Mark Brown <broonie@kernel.org> Link: https://lore.kernel.org/r/1587844788-33997-1-git-send-email-sanju.mehta@amd.com Signed-off-by: Mark Brown <broonie@kernel.org>
2020-04-25 14:59:48 -05:00
spi: amd: switch to use modern name Change legacy name master to modern name host or controller. No functional changed. Signed-off-by: Yang Yingliang <yangyingliang@huawei.com> Link: https://lore.kernel.org/r/20230728093221.3312026-2-yangyingliang@huawei.com Signed-off-by: Mark Brown <broonie@kernel.org>
2023-07-28 17:32:01 +08:00
spi: spi_amd: Enable dual and quad I/O modes The current spi_amd driver only supports single I/O mode, despite the AMD SPI controller's capability for dual and quad I/O modes for read operations. And AMD SPI0 controller has limited support for quad mode write operations. Update the SPI-MEM support function to reflect these hardware capabilities. Co-developed-by: Krishnamoorthi M <krishnamoorthi.m@amd.com> Signed-off-by: Krishnamoorthi M <krishnamoorthi.m@amd.com> Co-developed-by: Akshata MukundShetty <akshata.mukundshetty@amd.com> Signed-off-by: Akshata MukundShetty <akshata.mukundshetty@amd.com> Signed-off-by: Raju Rangoju <Raju.Rangoju@amd.com> Link: https://patch.msgid.link/20240925133644.2922359-3-Raju.Rangoju@amd.com Signed-off-by: Mark Brown <broonie@kernel.org>
2024-09-25 19:06:38 +05:30
spi: amd: switch to use modern name Change legacy name master to modern name host or controller. No functional changed. Signed-off-by: Yang Yingliang <yangyingliang@huawei.com> Link: https://lore.kernel.org/r/20230728093221.3312026-2-yangyingliang@huawei.com Signed-off-by: Mark Brown <broonie@kernel.org>
2023-07-28 17:32:01 +08:00
spi: spi_amd: Add support for SPI MEM framework Add support to the SPI controller driver to use SPI MEM framework. SPI subsystem utilizing the SPI memory operations allows to re-use SPI controller drivers for both SPI NOR devices, regular SPI devices as well as SPI NAND devices. Add below functions of spi_mem_ops to support SPI MEM framework - exec-op(): to execute the memory operations. - supports_op(): to check if the memory operation is supported. - adjust_op_size(): to split data transfers so that they don’t exceed the max transfer size supported by the controller. Suggested-by: Sudheesh Mavila <sudheesh.mavila@amd.com> Co-developed-by: Krishnamoorthi M <krishnamoorthi.m@amd.com> Signed-off-by: Krishnamoorthi M <krishnamoorthi.m@amd.com> Co-developed-by: Akshata MukundShetty <akshata.mukundshetty@amd.com> Signed-off-by: Akshata MukundShetty <akshata.mukundshetty@amd.com> Signed-off-by: Raju Rangoju <Raju.Rangoju@amd.com> Link: https://msgid.link/r/20240229134544.3461757-1-Raju.Rangoju@amd.com Signed-off-by: Mark Brown <broonie@kernel.org>
2024-02-29 19:15:44 +05:30
spi: amd: Support per spi-mem operation frequency switches Every ->exec_op() call correctly configures the spi bus speed to the maximum allowed frequency for the memory using the constant spi default parameter. Since we can now have per-operation constraints, let's use the value that comes from the spi-mem operation structure instead. In case there is no specific limitation for this operation, the default spi device value will be given anyway. This controller however performed a frequency check, which is also observed during the ->check_op() phase. The per-operation frequency capability is thus advertised to the spi-mem core. Cc: Sanjay R Mehta <sanju.mehta@amd.com> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> Link: https://patch.msgid.link/20241224-winbond-6-11-rc1-quad-support-v2-3-ad218dbc406f@bootlin.com Signed-off-by: Mark Brown <broonie@kernel.org>
2024-12-24 18:05:48 +01:00
spi: amd: switch to use modern name Change legacy name master to modern name host or controller. No functional changed. Signed-off-by: Yang Yingliang <yangyingliang@huawei.com> Link: https://lore.kernel.org/r/20230728093221.3312026-2-yangyingliang@huawei.com Signed-off-by: Mark Brown <broonie@kernel.org>
2023-07-28 17:32:01 +08:00
spi: spi-amd: Add AMD SPI controller driver support This driver supports SPI Controller for AMD SOCs.This driver supports SPI operations using FIFO mode of transfer. Signed-off-by: Sanjay R Mehta <sanju.mehta@amd.com> Signed-off-by: Mark Brown <broonie@kernel.org> Link: https://lore.kernel.org/r/1587844788-33997-1-git-send-email-sanju.mehta@amd.com Signed-off-by: Mark Brown <broonie@kernel.org>
2020-04-25 14:59:48 -05:00
spi: amd: switch to use modern name Change legacy name master to modern name host or controller. No functional changed. Signed-off-by: Yang Yingliang <yangyingliang@huawei.com> Link: https://lore.kernel.org/r/20230728093221.3312026-2-yangyingliang@huawei.com Signed-off-by: Mark Brown <broonie@kernel.org>
2023-07-28 17:32:01 +08:00
spi: amd: Make use of devm_spi_alloc_master() Make use of the devm variant of spi_alloc_master() in order to cleanup and simplify the error handling in the probe function by getting rid of the goto statements. Signed-off-by: Cristian Ciocaltea <cristian.ciocaltea@collabora.com> Link: https://lore.kernel.org/r/20220706100626.1234731-3-cristian.ciocaltea@collabora.com Signed-off-by: Mark Brown <broonie@kernel.org>
2022-07-06 13:06:23 +03:00
spi: amd: Make use of dev_err_probe() Simplify the error handling in probe function by switching from dev_err() to dev_err_probe(). Signed-off-by: Cristian Ciocaltea <cristian.ciocaltea@collabora.com> Link: https://lore.kernel.org/r/20220706100626.1234731-4-cristian.ciocaltea@collabora.com Signed-off-by: Mark Brown <broonie@kernel.org>
2022-07-06 13:06:24 +03:00
spi: spi-amd: Add AMD SPI controller driver support This driver supports SPI Controller for AMD SOCs.This driver supports SPI operations using FIFO mode of transfer. Signed-off-by: Sanjay R Mehta <sanju.mehta@amd.com> Signed-off-by: Mark Brown <broonie@kernel.org> Link: https://lore.kernel.org/r/1587844788-33997-1-git-send-email-sanju.mehta@amd.com Signed-off-by: Mark Brown <broonie@kernel.org>
2020-04-25 14:59:48 -05:00
spi: spi_amd: Add HIDDMA basic read support SPI index mode has hardware limitation of reading only 64 bytes per transaction due to fixed number of FIFO registers. This constraint leads to performance issues when reading data from NAND/NOR flash devices, as the controller must issue multiple requests to read 64-byte chunks, even if the slave can send up to 2 or 4 KB in single transaction. The AMD HID2 SPI controller supports DMA mode, which allows reading up to 4 KB of data in single transaction. This patch introduces changes to implement HID2 DMA read support for the HID2 SPI controller. Co-developed-by: Krishnamoorthi M <krishnamoorthi.m@amd.com> Signed-off-by: Krishnamoorthi M <krishnamoorthi.m@amd.com> Co-developed-by: Akshata MukundShetty <akshata.mukundshetty@amd.com> Signed-off-by: Akshata MukundShetty <akshata.mukundshetty@amd.com> Signed-off-by: Raju Rangoju <Raju.Rangoju@amd.com> Link: https://patch.msgid.link/20240925133644.2922359-9-Raju.Rangoju@amd.com Signed-off-by: Mark Brown <broonie@kernel.org>
2024-09-25 19:06:44 +05:30
spi: spi-amd: Add AMD SPI controller driver support This driver supports SPI Controller for AMD SOCs.This driver supports SPI operations using FIFO mode of transfer. Signed-off-by: Sanjay R Mehta <sanju.mehta@amd.com> Signed-off-by: Mark Brown <broonie@kernel.org> Link: https://lore.kernel.org/r/1587844788-33997-1-git-send-email-sanju.mehta@amd.com Signed-off-by: Mark Brown <broonie@kernel.org>
2020-04-25 14:59:48 -05:00
spi: spi_amd: Add PCI-based driver for AMD HID2 SPI controller Register a new driver(spi_amd_pci) for the HID2 SPI controller using the PCI ID of the LPC bridge device. Add a new common probe function in spi_amd driver to encapsulate the code required for registering the controller driver. This function will be utilized by both the existing ACPI driver and the newly introduced PCI-based driver for the HID2 SPI controller. The MMIO register base address of the HID2 SPI controller can be obtained from the PCI LPC bridge registers. By implementing these changes, the DMA buffer will be correctly associated with the LPC bridge device, preventing IO_PAGE_FAULT caused by IOMMU when the LPC bridge attempts DMA operations on addresses owned by the HID2 SPI controller. Co-developed-by: Krishnamoorthi M <krishnamoorthi.m@amd.com> Signed-off-by: Krishnamoorthi M <krishnamoorthi.m@amd.com> Co-developed-by: Akshata MukundShetty <akshata.mukundshetty@amd.com> Signed-off-by: Akshata MukundShetty <akshata.mukundshetty@amd.com> Signed-off-by: Raju Rangoju <Raju.Rangoju@amd.com> Link: https://patch.msgid.link/20250402121514.2941334-1-Raju.Rangoju@amd.com Signed-off-by: Mark Brown <broonie@kernel.org>
2025-04-02 17:45:14 +05:30
spi: spi_amd: Remove the use of dev_err_probe() The dev_err_probe() doesn't do anything when error is '-ENOMEM'. Therefore, remove the useless call to dev_err_probe(), and just return the value instead. Signed-off-by: Xichao Zhao <zhao.xichao@vivo.com> Link: https://patch.msgid.link/20250819092044.549464-2-zhao.xichao@vivo.com Signed-off-by: Mark Brown <broonie@kernel.org>
2025-08-19 17:20:38 +08:00
spi: spi_amd: Add PCI-based driver for AMD HID2 SPI controller Register a new driver(spi_amd_pci) for the HID2 SPI controller using the PCI ID of the LPC bridge device. Add a new common probe function in spi_amd driver to encapsulate the code required for registering the controller driver. This function will be utilized by both the existing ACPI driver and the newly introduced PCI-based driver for the HID2 SPI controller. The MMIO register base address of the HID2 SPI controller can be obtained from the PCI LPC bridge registers. By implementing these changes, the DMA buffer will be correctly associated with the LPC bridge device, preventing IO_PAGE_FAULT caused by IOMMU when the LPC bridge attempts DMA operations on addresses owned by the HID2 SPI controller. Co-developed-by: Krishnamoorthi M <krishnamoorthi.m@amd.com> Signed-off-by: Krishnamoorthi M <krishnamoorthi.m@amd.com> Co-developed-by: Akshata MukundShetty <akshata.mukundshetty@amd.com> Signed-off-by: Akshata MukundShetty <akshata.mukundshetty@amd.com> Signed-off-by: Raju Rangoju <Raju.Rangoju@amd.com> Link: https://patch.msgid.link/20250402121514.2941334-1-Raju.Rangoju@amd.com Signed-off-by: Mark Brown <broonie@kernel.org>
2025-04-02 17:45:14 +05:30
spi: amd: Set correct bus number in ACPI probe path On platforms where the HID2 SPI controller (AMDI0063) is enumerated via ACPI instead of PCI, amd_spi_probe() unconditionally sets bus_num to 0, while the PCI probe path assigns bus_num 2 for HID2 controller. Align the ACPI probe path to use the same bus number so that userspace and SPI client drivers see a consistent bus assignment regardless of the enumeration method. Fixes: b644c2776652 ("spi: spi_amd: Add PCI-based driver for AMD HID2 SPI controller") Cc: stable@vger.kernel.org # v6.16+ Signed-off-by: Krishnamoorthi M <krishnamoorthi.m@amd.com> Link: https://patch.msgid.link/20260507180051.4158674-1-krishnamoorthi.m@amd.com Signed-off-by: Mark Brown <broonie@kernel.org>
2026-05-07 23:30:51 +05:30
spi: spi_amd: Add PCI-based driver for AMD HID2 SPI controller Register a new driver(spi_amd_pci) for the HID2 SPI controller using the PCI ID of the LPC bridge device. Add a new common probe function in spi_amd driver to encapsulate the code required for registering the controller driver. This function will be utilized by both the existing ACPI driver and the newly introduced PCI-based driver for the HID2 SPI controller. The MMIO register base address of the HID2 SPI controller can be obtained from the PCI LPC bridge registers. By implementing these changes, the DMA buffer will be correctly associated with the LPC bridge device, preventing IO_PAGE_FAULT caused by IOMMU when the LPC bridge attempts DMA operations on addresses owned by the HID2 SPI controller. Co-developed-by: Krishnamoorthi M <krishnamoorthi.m@amd.com> Signed-off-by: Krishnamoorthi M <krishnamoorthi.m@amd.com> Co-developed-by: Akshata MukundShetty <akshata.mukundshetty@amd.com> Signed-off-by: Akshata MukundShetty <akshata.mukundshetty@amd.com> Signed-off-by: Raju Rangoju <Raju.Rangoju@amd.com> Link: https://patch.msgid.link/20250402121514.2941334-1-Raju.Rangoju@amd.com Signed-off-by: Mark Brown <broonie@kernel.org>
2025-04-02 17:45:14 +05:30
spi: spi-amd: Add AMD SPI controller driver support This driver supports SPI Controller for AMD SOCs.This driver supports SPI operations using FIFO mode of transfer. Signed-off-by: Sanjay R Mehta <sanju.mehta@amd.com> Signed-off-by: Mark Brown <broonie@kernel.org> Link: https://lore.kernel.org/r/1587844788-33997-1-git-send-email-sanju.mehta@amd.com Signed-off-by: Mark Brown <broonie@kernel.org>
2020-04-25 14:59:48 -05:00
spi: spi-amd: Do not define 'struct acpi_device_id' when !CONFIG_ACPI Since ACPI_PTR() is used to NULLify the value when !CONFIG_ACPI, struct 'spi_acpi_match' becomes defined but unused. Fixes the following W=1 kernel build warning(s): drivers/spi/spi-amd.c:297:36: warning: ‘spi_acpi_match’ defined but not used [-Wunused-const-variable=] 297 | static const struct acpi_device_id spi_acpi_match[] = { | ^~~~~~~~~~~~~~ Signed-off-by: Lee Jones <lee.jones@linaro.org> Cc: Sanjay R Mehta <sanju.mehta@amd.com> Link: https://lore.kernel.org/r/20200717135424.2442271-15-lee.jones@linaro.org Signed-off-by: Mark Brown <broonie@kernel.org>
2020-07-17 14:54:24 +01:00
spi: spi-amd: Add AMD SPI controller driver support This driver supports SPI Controller for AMD SOCs.This driver supports SPI operations using FIFO mode of transfer. Signed-off-by: Sanjay R Mehta <sanju.mehta@amd.com> Signed-off-by: Mark Brown <broonie@kernel.org> Link: https://lore.kernel.org/r/1587844788-33997-1-git-send-email-sanju.mehta@amd.com Signed-off-by: Mark Brown <broonie@kernel.org>
2020-04-25 14:59:48 -05:00
spi: amd: Add support for version AMDI0062 Add support for the AMD SPI controller version AMDI0062. Do this in a modular way where's easy to add new versions. Signed-off-by: André Almeida <andrealmeid@collabora.com> Link: https://lore.kernel.org/r/20220211143155.75513-4-andrealmeid@collabora.com Signed-off-by: Mark Brown <broonie@kernel.org>
2022-02-11 11:31:55 -03:00
spi: spi_amd: Add support for HID2 SPI controller AMD SoC has HID2 SPI controller in addition to the existing SPI0 controller(AMDI0062). Add HID2 SPI controller's ACPI ID AMDI0063 with its version ID to the list of supported devices. Use the version ID to differentiate the register offsets. And, the AMD HID2 SPI controller supports DMA read, allowing for up to 4 KB of data to be read in single transaction. Update the SPI-MEM support function to reflect this capability. Co-developed-by: Krishnamoorthi M <krishnamoorthi.m@amd.com> Signed-off-by: Krishnamoorthi M <krishnamoorthi.m@amd.com> Co-developed-by: Akshata MukundShetty <akshata.mukundshetty@amd.com> Signed-off-by: Akshata MukundShetty <akshata.mukundshetty@amd.com> Signed-off-by: Raju Rangoju <Raju.Rangoju@amd.com> Link: https://patch.msgid.link/20240925133644.2922359-7-Raju.Rangoju@amd.com Signed-off-by: Mark Brown <broonie@kernel.org>
2024-09-25 19:06:42 +05:30
spi: spi-amd: Add AMD SPI controller driver support This driver supports SPI Controller for AMD SOCs.This driver supports SPI operations using FIFO mode of transfer. Signed-off-by: Sanjay R Mehta <sanju.mehta@amd.com> Signed-off-by: Mark Brown <broonie@kernel.org> Link: https://lore.kernel.org/r/1587844788-33997-1-git-send-email-sanju.mehta@amd.com Signed-off-by: Mark Brown <broonie@kernel.org>
2020-04-25 14:59:48 -05:00
spi: spi-amd: Do not define 'struct acpi_device_id' when !CONFIG_ACPI Since ACPI_PTR() is used to NULLify the value when !CONFIG_ACPI, struct 'spi_acpi_match' becomes defined but unused. Fixes the following W=1 kernel build warning(s): drivers/spi/spi-amd.c:297:36: warning: ‘spi_acpi_match’ defined but not used [-Wunused-const-variable=] 297 | static const struct acpi_device_id spi_acpi_match[] = { | ^~~~~~~~~~~~~~ Signed-off-by: Lee Jones <lee.jones@linaro.org> Cc: Sanjay R Mehta <sanju.mehta@amd.com> Link: https://lore.kernel.org/r/20200717135424.2442271-15-lee.jones@linaro.org Signed-off-by: Mark Brown <broonie@kernel.org>
2020-07-17 14:54:24 +01:00
spi: spi-amd: Add AMD SPI controller driver support This driver supports SPI Controller for AMD SOCs.This driver supports SPI operations using FIFO mode of transfer. Signed-off-by: Sanjay R Mehta <sanju.mehta@amd.com> Signed-off-by: Mark Brown <broonie@kernel.org> Link: https://lore.kernel.org/r/1587844788-33997-1-git-send-email-sanju.mehta@amd.com Signed-off-by: Mark Brown <broonie@kernel.org>
2020-04-25 14:59:48 -05:00
spi: amd: Fix building without ACPI enabled Commit 209043554915 ("spi: amd: Add support for version AMDI0062") removed the cast ACPI_PTR() for no good reason. This wrapper is important to make sure that the driver can be compiled with or without CONFIG_ACPI enabled, useful for compiling test. Give back the cast so compilation works again. Fixes: 209043554915 ("spi: amd: Add support for version AMDI0062") Signed-off-by: André Almeida <andrealmeid@collabora.com> Link: https://lore.kernel.org/r/20220216162719.116062-1-andrealmeid@collabora.com Signed-off-by: Mark Brown <broonie@kernel.org>
2022-02-16 13:27:19 -03:00
spi: spi-amd: Add AMD SPI controller driver support This driver supports SPI Controller for AMD SOCs.This driver supports SPI operations using FIFO mode of transfer. Signed-off-by: Sanjay R Mehta <sanju.mehta@amd.com> Signed-off-by: Mark Brown <broonie@kernel.org> Link: https://lore.kernel.org/r/1587844788-33997-1-git-send-email-sanju.mehta@amd.com Signed-off-by: Mark Brown <broonie@kernel.org>
2020-04-25 14:59:48 -05:00