drm/i915/hsw, bdw: Add irq_pipe_mask, has_vga power well attributes

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The pattern of a power well backing a set of pipe IRQ or VGA
functionality applies to all HSW+ platforms. Using power well attributes
instead of platform checks to decide whether to init/reset pipe IRQs and
VGA correspondingly is cleaner and it allows us to unify the HSW/BDW and
GEN9+ power well code in follow-up patches.

Also use u8 for pipe_mask in related helpers to match the type in the
power well struct.

v2:
- Use u8 instead of u32 for irq_pipe_mask. (Ville)

v3:
- Use u8 for pipe_mask in related helpers too for clarity.

Signed-off-by: Imre Deak <imre.deak@intel.com>
Reviewed-by: Arkadiusz Hiler <arkadiusz.hiler@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20170712155413.29839-1-imre.deak@intel.com
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>

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Imre Deak 2017-07-12 18:54:13 +03:00 • committed by Daniel Vetter

parent 1af474fef2

commit 001bd2cb17

4 changed files with 31 additions and 17 deletions

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6

drivers/gpu/drm/i915/i915_drv.h

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4

drivers/gpu/drm/i915/i915_irq.c

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4

drivers/gpu/drm/i915/intel_drv.h

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34

drivers/gpu/drm/i915/intel_runtime_pm.c

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