drm/i915/chv: Update Cherryview DPLL changes to support Port D. v2

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The additional DPLL registers added to support Port D.  Besides, add
some new PHY control and status registers based on B-spec.

v2: Based on Ville review
	- Corrected DPIO_PHY_STATUS offset and name.
    - Rebase based on upstream change after introduce enum dpio_phy and
      enum dpio_channel.

v3: Rebased on top of Antti's 3-pipe prep patch. Note that the new offsets for
the DPLL registers aren't in place yet, so this introduces a slight regression.
But since 3 pipe support isn't fully enabled yet anyaway in -internal this
shouldn't matter too much.

Signed-off-by: Chon Ming Lee <chon.ming.lee@intel.com>
Reviewed-by: Imre Deak <imre.deak@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>

...

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Chon Ming Lee 2014-04-09 13:28:15 +03:00 • committed by Daniel Vetter

parent a09cadddde

commit 00fc31b72e

3 changed files with 16 additions and 2 deletions

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6

drivers/gpu/drm/i915/i915_reg.h

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11

drivers/gpu/drm/i915/intel_display.c

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1

drivers/gpu/drm/i915/intel_drv.h

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