soc/tegra: fuse: speedo-tegra210: Update speedo IDs

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[ Upstream commit ce27c9c212 ]

Existing code only sets CPU and GPU speedo IDs 0 and 1. The CPU DVFS
code supports 11 IDs and nouveau supports 5. This aligns with what the
downstream vendor kernel supports. Align SKUs with the downstream list.

The Tegra210 CVB tables were added in the first referenced fixes commit.
Since then, all Tegra210 SoCs have tried to scale to 1.9 GHz, when the
supported devkits are only supposed to scale to 1.5 or 1.7 GHZ.
Overclocking should not be the default state.

Fixes: 2b2dbc2f94 ("clk: tegra: dfll: add CVB tables for Tegra210")
Fixes: 579db6e5d9 ("arm64: tegra: Enable DFLL support on Jetson Nano")
Signed-off-by: Aaron Kling <webgeek1234@gmail.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Signed-off-by: Sasha Levin <sashal@kernel.org>

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Aaron Kling 2025-09-23 11:58:05 -05:00 • committed by Greg Kroah-Hartman

parent 9c58e23af9

commit 020ecb16e5

1 changed files with 43 additions and 19 deletions

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drivers/soc/tegra/fuse/speedo-tegra210.c

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