clk: tegra: dfll: add CVB tables for Tegra210

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Add CVB tables with different chip characterization, so that we can
generate the customize OPP table that suitable for different chips with
different SKUs.

The parameter 'tune_high_min_millivolts' is first time introduced in
this patch, which didn't use in the DFLL driver for clock and voltage
tuning before. It will be used later when DFLL in high voltage range.

Signed-off-by: Joseph Lo <josephl@nvidia.com>
Acked-by: Jon Hunter <jonathanh@nvidia.com>
Acked-by: Stephen Boyd <sboyd@kernel.org>
Signed-off-by: Thierry Reding <treding@nvidia.com>

...

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Joseph Lo 2019-01-04 11:06:51 +08:00 • committed by Thierry Reding

parent f7ebf8874c

commit 2b2dbc2f94

2 changed files with 427 additions and 0 deletions

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426

drivers/clk/tegra/clk-tegra124-dfll-fcpu.c

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1

drivers/clk/tegra/cvb.h

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