perf/x86/intel: Constrain Panther Cove UOPS_DISPATCHED events to PMCs 0-3

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Per the latest Panther Cove event definitions, the following events are
only supported on PMCs 0-3:

- UOPS_DISPATCHED.INT_EU_ALL (0x1b2)
- UOPS_DISPATCHED.ALU (0x2b2)

Add explicit event constraints for these two events so scheduling does
not place them on unsupported counters.

Fixes: d345b6bb88 ("perf/x86/intel: Add core PMU support for DMR")
Signed-off-by: Dapeng Mi <dapeng1.mi@linux.intel.com>
Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org>
Signed-off-by: Ingo Molnar <mingo@kernel.org>
Cc: <stable@vger.kernel.org> # v7.0+
Link: https://patch.msgid.link/20260917015234.981153-10-dapeng1.mi@linux.intel.com

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Dapeng Mi 2026-09-17 09:52:31 +08:00 • committed by Ingo Molnar

parent 858b37ca19

commit 04a7ef3b7a

1 changed files with 2 additions and 0 deletions

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arch/x86/events/intel/core.c

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