drm/amd/display: Clear lane settings after LTTPRs have been trained

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[Why]
The voltage swing has to start from the minimum level when transmit TPS1 over
Main-Link in clock recovery sequence.
The lane settings from current design will inherit the existing VS/PE values
that could be adjusted by Repeater X, and to use the adjusted voltage swing level
in Repeater X-1 or DPRX could violate DP specs.

[How]
To reset VS from lane settings after LTTPRs have been trained to meet the requirement.

Signed-off-by: Martin Tsai <martin.tsai@amd.com>
Reviewed-by: Wenjing Liu <Wenjing.Liu@amd.com>
Acked-by: Bindu Ramamurthy <bindu.r@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

...

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Martin Tsai 2021-06-08 13:48:32 +08:00 • committed by Alex Deucher

parent 5d9e7fe8ef

commit 068312559d

1 changed files with 4 additions and 0 deletions

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drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c

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