clk: renesas: r9a07g044: Add WDT clock and reset entries

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Add WDT{0,1,2} clock and reset entries to CPG driver.

Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Link: https://lore.kernel.org/r/20211104160858.15550-4-biju.das.jz@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>

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Biju Das 2021-11-04 16:08:57 +00:00 • committed by Geert Uytterhoeven

parent a0d2a2c673

commit 073da9e7c7

1 changed files with 15 additions and 0 deletions

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drivers/clk/renesas/r9a07g044-cpg.c

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