clk: renesas: r9a09g056: Add clock and reset entries for ISP

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Add entries detailing the clocks and resets for the ISP in the
RZ/V2N SoC.

Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://patch.msgid.link/20251023210724.666476-4-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>

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Lad Prabhakar 2025-10-23 22:07:24 +01:00 • committed by Geert Uytterhoeven

parent 861df8792c

commit 07525a693a

1 changed files with 14 additions and 0 deletions

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drivers/clk/renesas/r9a09g056-cpg.c

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