clk: renesas: r9a09g056: Add support for PLLVDO, CRU clocks, and resets

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Add support for the PLLVDO clock and its related CRU clocks and reset
entries in the R9A09G056 CPG driver. Introduce `CLK_PLLVDO` and associated
clocks like `CLK_PLLVDO_CRU0` and `CLK_PLLVDO_CRU1`, along with their
corresponding dividers.

Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://patch.msgid.link/20251023210724.666476-3-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>

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Lad Prabhakar 2025-10-23 22:07:23 +01:00 • committed by Geert Uytterhoeven

parent d64522b54b

commit 861df8792c

1 changed files with 31 additions and 0 deletions

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drivers/clk/renesas/r9a09g056-cpg.c

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