drm/amd/display: Pass min page size from SOC BB to dml2_1 plane config

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[Why]
Like dml2_0 this isn't guaranteed to be constant for every ASIC.

This can cause corruption or underflow for linear surfaces due to a
wrong PTE_ROW_HEIGHT_LINEAR value if not correctly specified.

[How]
Like dml2_0 pass in the SOC bb into the plane configuration population
functions.

Set both GPUVM and HostVM page sizes in the overrides.

Reviewed-by: Dillon Varone <dillon.varone@amd.com>
Signed-off-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>
Signed-off-by: Roman Li <roman.li@amd.com>
Tested-by: Dan Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

...

This commit is contained in:

Nicholas Kazlauskas 2026-03-19 14:34:56 -04:00 • committed by Alex Deucher

parent 5a89553231

commit 07ac59230d

1 changed files with 15 additions and 6 deletions

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21

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/dml21_translation_helper.c

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