clk: tegra: Add PLL post divider table

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Some PLLs in Tegra114 don't use a power of 2 mapping for the post divider.
Introduce a table based approach and switch PLLU to it.

Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
Acked-by: Mike Turquette <mturquette@linaro.org>
Signed-off-by: Stephen Warren <swarren@nvidia.com>

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Peter De Schrijver 2013-04-03 17:40:39 +03:00 • committed by Stephen Warren

parent 7ba28813b4

commit 0b6525acd1

4 changed files with 59 additions and 6 deletions

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38

drivers/clk/tegra/clk-pll.c

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7

drivers/clk/tegra/clk-tegra20.c

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7

drivers/clk/tegra/clk-tegra30.c

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13

drivers/clk/tegra/clk.h

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