drm/i915/lt_phy: Add verification for lt phy pll dividers

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Add verification for lt phy pll dividers during boot. The port clock
is calculated from pll dividers and compared against the requested
port clock value. If there are a difference exceeding +-1 kHz an
drm_warn() is thrown out to indicate possible pll divider mismatch.

v2:
- Move the LT_PHY_PLL_PARAMS -> LT_PHY_PLL_DP/HDMI_PARAMS change
  earlier.
- Use tables[i].name != NULL as a terminating condition.
- Use state vs. params term consistently in intel_c10pll_verify_clock()
  and intel_c20pll_verify_clock().

Signed-off-by: Mika Kahola <mika.kahola@intel.com>
Reviewed-by: Suraj Kandpal <suraj.kandpal@intel.com>
Link: https://patch.msgid.link/20260119093757.2850233-13-mika.kahola@intel.com

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This commit is contained in:

Mika Kahola 2026-01-19 09:37:53 +00:00

parent 58213c1d78

commit 10d187b356

3 changed files with 66 additions and 0 deletions

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2

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

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63

drivers/gpu/drm/i915/display/intel_lt_phy.c

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1

drivers/gpu/drm/i915/display/intel_lt_phy.h

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