drm/i915/cx0: Verify C10/C20 pll dividers

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Add verification for pll table dividers. The port clock
is computed based on pll tables and, for hdmi case, the
algorithmic model is applied to calculate pll dividers.
If port clock differs more than +-1 kHz from expected value
an drm_warn() is thrown and pll divider differences are
printed out for debugging purposes.

v2:
- Move clock derivation from dividers in intel_cx0pll_enable()
  earlier in the patchset.
- Keep intel_cx0_pll_power_save_wa() in intel_dpll_sanitize_state()
- Use tables[i].name != NULL as a terminating condition.
- Drop duplicate intel_cx0pll_clock_matches() declaration in header.
- Use state vs. params term consistently in intel_c10pll_verify_clock()
  and intel_c20pll_verify_clock().

Signed-off-by: Mika Kahola <mika.kahola@intel.com>
Reviewed-by: Suraj Kandpal <suraj.kandpal@intel.com>
Link: https://patch.msgid.link/20260119093757.2850233-12-mika.kahola@intel.com

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This commit is contained in:

Mika Kahola 2026-01-19 09:37:52 +00:00

parent 50ad932880

commit 58213c1d78

3 changed files with 130 additions and 1 deletions

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121

drivers/gpu/drm/i915/display/intel_cx0_phy.c

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1

drivers/gpu/drm/i915/display/intel_cx0_phy.h

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9

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

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