clk: renesas: rcar-gen3: Parameterise Z and Z2 clock offset

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Parameterise the offset of control bits within the FRQCRC register
for Z and Z2 clocks.

This is in preparation for supporting the Z2 clock on the R-Car E3
(r8a77990) SoC which uses a different offset for control bits to
other, already, supported SoCs.

As suggested by Geert Uytterhoeven.

Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>

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This commit is contained in:

Simon Horman 2019-03-25 17:35:51 +01:00 • committed by Geert Uytterhoeven

parent 20cc05ba04

commit 10d9ea5100

6 changed files with 13 additions and 20 deletions

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4

drivers/clk/renesas/r8a774a1-cpg-mssr.c

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4

drivers/clk/renesas/r8a7795-cpg-mssr.c

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4

drivers/clk/renesas/r8a7796-cpg-mssr.c

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drivers/clk/renesas/r8a77965-cpg-mssr.c

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15

drivers/clk/renesas/rcar-gen3-cpg.c

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drivers/clk/renesas/rcar-gen3-cpg.h

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