clk: sunxi-ng: sun8i: a83t: Add /2 fixed post divider to audio PLL

Browse source

On the A83T, the audio PLL should have its div1 set to 0, or /1, and
div2 set to 1, or /2. This setting is the default, and is required
to match the sigma-delta modulation parameters from the BSP kernel.

This patch adds a /2 fixed post divider to the audio PLL, and fixes
the enforced d1 & d2 values. This also resolves the mismatch between
the values mentioned in the comment for the audio PLL, and the actual
enforced values.

Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>

...

This commit is contained in:

Chen-Yu Tsai 2017-12-08 16:35:11 +08:00 • committed by Maxime Ripard

parent 7d333ef1cc

commit 10e6eb4f2c

1 changed files with 6 additions and 3 deletions

Show all changes Ignore whitespace when comparing lines Ignore changes in amount of whitespace Ignore changes in whitespace at EOL

Download patch file Download diff file Expand all files Collapse all files

9

drivers/clk/sunxi-ng/ccu-sun8i-a83t.c

View file