clk: sunxi-ng: Support fixed post-dividers on NM style clocks

Browse source

On the A83T, the audio PLL should have its div1 set to 0, or /1, and
div2 set to 1, or /2. This setting is the default, and is required
to match the sigma-delta modulation parameters from the BSP kernel.

To do this, we first add fixed post-divider to the NM style clocks,
which is the type of clock the audio PLL clock is modeled into.

Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>

...

This commit is contained in:

Chen-Yu Tsai 2017-12-08 16:35:10 +08:00 • committed by Maxime Ripard

parent 83fe3be4d1

commit 7d333ef1cc

2 changed files with 39 additions and 13 deletions

Show all changes Ignore whitespace when comparing lines Ignore changes in amount of whitespace Ignore changes in whitespace at EOL

Download patch file Download diff file Expand all files Collapse all files

52

drivers/clk/sunxi-ng/ccu_nm.c

View file

2

drivers/clk/sunxi-ng/ccu_nm.h

View file