drm/i915/dmc: Define flip queue related PIPEDMC registers

Browse source

Add the register definitions for a bunch of flip queue related
PIPEDMC registers.

v2: The layout of flip queue entries changed on PTL
    Bump the DMC_FQ_W2_PTS_CFG_SEL bitfields sizes (Uma)
    Reduce the scanlines to 21 bits for now (Uma)
v3: Also define some undocumented DMC variables we need on PTL
v3: Drop PIPEDMC_FQ_CTRL_BUSY as it seems to no longer exist
    on LNL+
    Fix up some typos

Reviewed-by: Uma Shankar <uma.shankar@intel.com>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20250624170049.27284-4-ville.syrjala@linux.intel.com

...

This commit is contained in:

Ville Syrjälä 2025-06-24 20:00:43 +03:00

parent 9367e41483

commit 141b954cae

1 changed files with 190 additions and 0 deletions

Show all changes Ignore whitespace when comparing lines Ignore changes in amount of whitespace Ignore changes in whitespace at EOL

Download patch file Download diff file Expand all files Collapse all files

190

drivers/gpu/drm/i915/display/intel_dmc_regs.h

View file