cxl/port: Link the 'parent_dport' in portX/ and endpointX/ sysfs

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Similar to the justification in:

1b58b4cac6 ("cxl/port: Record parent dport when adding ports")

...userspace wants to know the routing information for ports for
calculating the memdev order for region creation among other things.
Cache the information the kernel discovers at enumeration time in a
'parent_dport' attribute to save userspace the time of trawling sysfs
to recover the same information.

Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Link: https://lore.kernel.org/r/167124082375.1626103.6047000000121298560.stgit@dwillia2-xfh.jf.intel.com
Signed-off-by: Dan Williams <dan.j.williams@intel.com>

...

This commit is contained in:

Dan Williams 2023-01-25 15:32:57 -08:00

parent af3ea9ab61

commit 172738bbcc

2 changed files with 44 additions and 0 deletions

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15

Documentation/ABI/testing/sysfs-bus-cxl

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29

drivers/cxl/core/port.c

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