clk: mediatek: Fix calculation of PLL rate settings

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Avoid u32 overflow when calculate post divider setting, and
increase the max post divider setting from 3 (/8) to 4 (/16).

Signed-off-by: James Liao <jamesjj.liao@mediatek.com>
Acked-by: Sascha Hauer <s.hauer@pengutronix.de>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>

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James Liao 2015-07-10 16:39:33 +08:00 • committed by Stephen Boyd

parent b3be457e58

commit 196de71a9d

1 changed files with 2 additions and 2 deletions

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drivers/clk/mediatek/clk-pll.c

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