clk: sunxi-ng: h6: fix bus clocks' divider position

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commit 2852bfbf4f upstream.

The bus clocks (AHB/APB) on Allwinner H6 have their second divider start
at bit 8, according to the user manual and the BSP code. However,
currently the divider offset is incorrectly set to 16, thus the divider
is not correctly read and the clock frequency is not correctly calculated.

Fix this bit offset on all affected bus clocks in ccu-sun50i-h6.

Cc: stable@vger.kernel.org # v4.17.y
Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>

...

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Icenowy Zheng 2018-08-09 01:19:52 +08:00 • committed by Greg Kroah-Hartman

parent 11ace0214b

commit 1a2502d376

1 changed files with 4 additions and 4 deletions

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drivers/clk/sunxi-ng/ccu-sun50i-h6.c

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