clk: renesas: r9a09g057: Remove entries for WDT{0,2,3}

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The HW user manual for the Renesas RZ/V2H(P) SoC specifies
that only the WDT1 IP is supposed to be used by Linux,
while the WDT{0,2,3} IPs are supposed to be used by the CM33
and CR8 cores.

Remove the clock and reset entries for WDT{0,2,3} to prevent
interfering with the CM33 and CR8 cores.

This change is harmless as only WDT1 is used by Linux, there
are no users for the WDT{0,2,3} cores.

Fixes: 3aeccbe081 ("clk: renesas: r9a09g057: Add clock and reset entries for GTM/RIIC/SDHI/WDT")
Signed-off-by: Fabrizio Castro <fabrizio.castro.jz@renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://patch.msgid.link/20260203124247.7320-4-fabrizio.castro.jz@renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>

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Fabrizio Castro 2026-02-03 12:42:47 +00:00 • committed by Geert Uytterhoeven

parent dc71d92f0d

commit 1b4f047dc4

1 changed files with 0 additions and 15 deletions

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drivers/clk/renesas/r9a09g057-cpg.c

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