clk: renesas: r9a09g056: Fix ordering of module clocks array

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The r9a09g056_mod_clks array is sorted by CPG_CLKON register number and
bit position.  Move the RSPI 0/1/2 module clock entries to their correct
position to restore the array sort order.

Fixes: 1f76689d17 ("clk: renesas: r9a09g056: Add entries for RSCIs")
Signed-off-by: Ovidiu Panait <ovidiu.panait.rb@renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://patch.msgid.link/20260125192706.27099-2-ovidiu.panait.rb@renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>

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Ovidiu Panait 2026-01-25 19:27:01 +00:00 • committed by Geert Uytterhoeven

parent 79cac2b8dc

commit dc71d92f0d

1 changed files with 18 additions and 18 deletions

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drivers/clk/renesas/r9a09g056-cpg.c

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