drm/i915: Compute WR PLL dividers dynamically

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Up to now, we were using a static table to match the clock frequency
with a (r2,n2,p) triplet. Despite this table being big, it's by no mean
comprehensive and we had to fall back to the closest frequency when the
requested TMDS clock wasn't in the table.

This patch computes (r2,n2,p) dynamically and get rid of The Big Table.

v2: Replace the floating point constant 1e6 by 1000000

Bugzilla: http://bugs.freedesktop.org/show_bug.cgi?id=58497
Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com> (v1)
Tested-by: Paulo Zanoni <paulo.r.zanoni@intel.com> (v1)
[danvet: s/        /^T/]
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>

...

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Damien Lespiau 2013-05-10 14:01:51 +01:00 • committed by Daniel Vetter

parent d89f207146

commit 1c0b85c566

1 changed files with 214 additions and 403 deletions

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drivers/gpu/drm/i915/intel_ddi.c

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