drm/i915: HSW FBC WaFbcDisableDpfcClockGating

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Display register 46500h bit 23 must be set to 1b for the entire time that
Frame Buffer Compression is enabled.

v2: Ville suggested to enable it back when disabling fbc to avoid wasting
    power.

v3: RMW to preserve other bits (by Ville)
v4: Fix from Ville: sed &/| at RMW
v5: Too far on sed.

Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@gmail.com>
[danvet: Insert missing space that checkpatch spotted.]
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>

...

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Rodrigo Vivi 2013-05-09 14:20:50 -03:00 • committed by Daniel Vetter

parent 285541647a

commit d89f207146

2 changed files with 13 additions and 0 deletions

Show all changes Ignore whitespace when comparing lines Ignore changes in amount of whitespace Ignore changes in whitespace at EOL

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3

drivers/gpu/drm/i915/i915_reg.h

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10

drivers/gpu/drm/i915/intel_pm.c

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