clk: imx5: Fix i.MX50 ESDHC clock registers

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The MUX bits for esdhc_{a,c,d}_sel are shifted by one bit within CSCMR1,
because esdhc_b_sel (ESDHC3_CLK_SEL in the Reference Manual) is extended
by one bit.

Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>

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Jonathan Neuschäfer 2019-03-26 19:22:58 +01:00 • committed by Shawn Guo

parent 639eb92531

commit 1e06250983

1 changed files with 30 additions and 10 deletions

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drivers/clk/imx/clk-imx51-imx53.c

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