clk: meson: axg: fix the od shift of the sys_pll

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According to the datasheet, the od shift of sys_pll is actually 16.

Fixes: 78b4af312f ('clk: meson-axg: add clock controller drivers')
Signed-off-by: Yixun Lan <yixun.lan@amlogic.com>
[fixed commit message]
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>

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Yixun Lan 2018-01-19 10:09:26 +08:00 • committed by Jerome Brunet

parent 6b71aceceb

commit 2fa9b361e5

1 changed files with 1 additions and 1 deletions

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drivers/clk/meson/axg.c

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