perf/x86/intel: Update event constraints and cache_extra_regsfor SPR

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Update perf hard-coded event constraints and cache_extra_regs[] for
Sapphire rapids according to the latest SPR perfmon events (v1.39).

Emerald Rapids (EMR) and Granite Rapids (GNR) share exactly same event
constraints and extra MSR values with SPR. No extra changes are needed
for EMR and GNR.

Please note the change could temporarily impact other platforms which
share the hard coded data structures, but it would be fixed in
subsequent patches soon.

SPR perfmon events:
https://github.com/intel/perfmon/blob/main/SPR/events/sapphirerapids_core.json

Signed-off-by: Dapeng Mi <dapeng1.mi@linux.intel.com>
Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org>
Link: https://patch.msgid.link/20260515061143.338553-3-dapeng1.mi@linux.intel.com

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Dapeng Mi 2026-05-15 14:11:34 +08:00 • committed by Peter Zijlstra

parent acc41cdcb0

commit 30d82ddee0

1 changed files with 14 additions and 9 deletions

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arch/x86/events/intel/core.c

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