perf/x86/intel: Update event constraints and cache_extra_regsfor ICX

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Update perf hard-coded event constraints and cache_extra_regs[] for
Icelake server according to the latest ICX perfmon events (v1.30).

Since the value of cache extra registers differs with previous
generations, introduce new snc_hw_cache_extra_regs[] to represent the
value of extra registers on ICX.

ICX perfmon events:
https://github.com/intel/perfmon/blob/main/ICX/events/icelakex_core.json

Signed-off-by: Dapeng Mi <dapeng1.mi@linux.intel.com>
Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org>
Link: https://patch.msgid.link/20260515061143.338553-2-dapeng1.mi@linux.intel.com

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Dapeng Mi 2026-05-15 14:11:33 +08:00 • committed by Peter Zijlstra

parent 5c3cdc74af

commit acc41cdcb0

1 changed files with 43 additions and 5 deletions

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arch/x86/events/intel/core.c

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