clk: renesas: rcar-gen4: Add support for fixed variable PLLs

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The custom clock driver that models PLL clocks on R-Car Gen4 supports
variable clocks, while PLL1 uses a similar control register layout, but
is read-only.

Extend the existing support to fixed clocks and PLL1, and introduce a
new clock type and helper macro to describe a fixed PLL.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
Link: https://lore.kernel.org/841fbb63d472c357b3ce291a5991db3b847f96d8.1721648548.git.geert+renesas@glider.be

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This commit is contained in:

Geert Uytterhoeven 2024-07-22 13:50:27 +02:00

parent 724620bd71

commit 3284ffb74c

2 changed files with 26 additions and 10 deletions

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32

drivers/clk/renesas/rcar-gen4-cpg.c

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4

drivers/clk/renesas/rcar-gen4-cpg.h

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