clk: renesas: rzg2l: Add support to handle coupled clocks

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The AXI and CHI clocks use the same register bit for controlling clock
output. Add a new clock type for coupled clocks, which sets the
CPG_CLKON_ETH.CLK[01]_ON bit when at least one clock is enabled, and
clears the bit only when both clocks are disabled.

Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Link: https://lore.kernel.org/r/20210922155145.28156-4-biju.das.jz@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>

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Biju Das 2021-09-22 16:51:44 +01:00 • committed by Geert Uytterhoeven

parent 70a4af3662

commit 32897e6fff

2 changed files with 81 additions and 1 deletions

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71

drivers/clk/renesas/rzg2l-cpg.c

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11

drivers/clk/renesas/rzg2l-cpg.h

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