perf/x86/intel: Update event constraints and cache_extra_regsfor LNL

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Update perf hard-coded event constraints and cache_extra_regs[] for
Lunarlake according to the latest LNL perfmon events (V1.22).

LNL introduces new extra register values for the OCR L3 cache events,
so introduce lnc_hw_cache_extra_regs[] and skt_hw_cache_extra_regs[] to
reflect the changes.

LNL perfmon events:
https://github.com/intel/perfmon/blob/main/LNL/events/lunarlake_lioncove_core.json
https://github.com/intel/perfmon/blob/main/LNL/events/lunarlake_skymont_core.json

Signed-off-by: Dapeng Mi <dapeng1.mi@linux.intel.com>
Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org>
Link: https://patch.msgid.link/20260515061143.338553-7-dapeng1.mi@linux.intel.com

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Dapeng Mi 2026-05-15 14:11:38 +08:00 • committed by Peter Zijlstra

parent e99fb45436

commit 331c3e4fa3

2 changed files with 59 additions and 11 deletions

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62

arch/x86/events/intel/core.c

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8

arch/x86/events/intel/ds.c

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