clk: tegra: Fix ISP clock modelling

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The 2 ISP clocks (ispa and ispb) share a mux/divider control. So model
this as 1 mux/divider clock and child gate clocks.

Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
Reviewed-by: Mikko Perttunen <mperttunen@nvidia.com>
Tested-by: Mikko Perttunen <mperttunen@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>

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Peter De Schrijver 2017-02-23 12:44:39 +02:00 • committed by Thierry Reding

parent 9326947f22

commit 34ac2c278b

4 changed files with 13 additions and 4 deletions

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1

drivers/clk/tegra/clk-id.h

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11

drivers/clk/tegra/clk-tegra-periph.c

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1

drivers/clk/tegra/clk-tegra210.c

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4

include/dt-bindings/clock/tegra210-car.h

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