clk: renesas: r9a07g044: Add SDHI clock and reset entries

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Add SDHI{0,1} mux, clock and reset entries to CPG driver.

Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Link: https://lore.kernel.org/r/20211007111434.8665-3-biju.das.jz@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>

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Biju Das 2021-10-07 12:14:34 +01:00 • committed by Geert Uytterhoeven

parent eaff33646f

commit 373bd6f487

2 changed files with 40 additions and 0 deletions

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36

drivers/clk/renesas/r9a07g044-cpg.c

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4

drivers/clk/renesas/rzg2l-cpg.h

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