clk: samsung: exynos5250: Fix parent of gate clocks from DISP1 domain

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This patch adds mux_aclk_200_disp1_sub mux clock, which according to SoC
documentation is the correct parent of DISP1 gate clocks.

Signed-off-by: Tomasz Figa <t.figa@samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
Tested-by: Tomasz Figa <t.figa@samsung.com>

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Tomasz Figa 2013-10-15 19:41:18 +02:00

parent 796d1f4cd6

commit 3818f11740

1 changed files with 8 additions and 6 deletions

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drivers/clk/samsung/clk-exynos5250.c

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