clk: renesas: Updates for v6.14

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- Add sound (SSI), remaining serial (SCIF), and ADC clocks, resets,
     and power domains on RZ/G3S,
   - Add system restart support on RZ/N1,
   - Add camera clocks and resets on RZ/V2H(P),
   - Add display clocks on R-Car V4M,
   - Miscellaneous fixes and improvements.
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Merge tag 'renesas-clk-for-v6.14-tag1' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers into clk-renesas

Pull Renesas clk driver udpates from Geert Uytterhoeven:

 - Add sound (SSI), remaining serial (SCIF), and ADC clocks, resets
   and power domains on Renesas RZ/G3S
 - Add system restart support on Renesas RZ/N1
 - Add camera clocks and resets on Renesas RZ/V2H(P)
 - Add display clocks on Renesas R-Car V4M

* tag 'renesas-clk-for-v6.14-tag1' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers:
  clk: renesas: r9a08g045: Add clocks, resets and power domain support for the ADC IP
  clk: renesas: r8a779h0: Add display clocks
  clk: renesas: r9a09g057: Add support for PLLVDO, CRU clocks, and resets
  clk: renesas: rzv2h: Add selective Runtime PM support for clocks
  clk: renesas: r9a06g032: Use BIT macro consistently
  clk: renesas: r9a06g032: Add restart handler
  clk: renesas: r9a08g045: Add clock, reset and power domain for the remaining SCIFs
  clk: renesas: r9a08g045: Add clocks, resets and power domains support for SSI
  clk: renesas: cpg-mssr: Fix 'soc' node handling in cpg_mssr_reserved_init()

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This commit is contained in:

Stephen Boyd 2024-12-20 15:44:41 -08:00

parent d3dcc98f65 f962745289

commit 39a72b4fed

7 changed files with 180 additions and 9 deletions

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4

drivers/clk/renesas/r8a779h0-cpg-mssr.c

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29

drivers/clk/renesas/r9a06g032-clocks.c

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drivers/clk/renesas/r9a08g045-cpg.c

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drivers/clk/renesas/r9a09g057-cpg.c

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drivers/clk/renesas/renesas-cpg-mssr.c

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drivers/clk/renesas/rzv2h-cpg.c

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18

drivers/clk/renesas/rzv2h-cpg.h

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