drm/i915: PIPE_CONTROL TLB invalidate requires CS stall

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"If ENABLED, PIPE_CONTROL command will flush the in flight data  written
out by render engine to Global Observation point on flush done. Also
Requires stall bit ([20] of DW1) set."

So set the stall bit to ensure proper invalidation.

Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Reviewed-by: Antti Koskipää <antti.koskipaa@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>

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Jesse Barnes 2012-10-25 12:15:47 -07:00 • committed by Daniel Vetter

parent 9a28977181

commit 3ac7831314

1 changed files with 1 additions and 1 deletions

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drivers/gpu/drm/i915/intel_ringbuffer.c

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