clk: meson: fix rate calculation of plls with a fractional part

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The rate of the parent should not be multiplied by 2 when the pll has a
fractional part. This is making the rate calculation of the gxl_hdmi_pll
wrong (and others as well). This multiplication is specific
to the hdmi_pll of gxbb and is most likely due to a multiplier sitting
in front of this particular pll.

Add a fixed factor clock in front on the gxbb pll and remove this constant
from the calculation to fix the problem

Fixes: 4a47295144 ("clk: meson: fractional pll support")
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>

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This commit is contained in:

Jerome Brunet 2018-01-19 16:55:27 +01:00

parent 69d9229327

commit 3c4fe763d6

3 changed files with 15 additions and 3 deletions

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1

drivers/clk/meson/clk-pll.c

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14

drivers/clk/meson/gxbb.c

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3

drivers/clk/meson/gxbb.h

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