clk: renesas: rcar-gen3: Correct parent clock of SYS-DMAC

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The clock sources of the AXI BUS clock (266.66 MHz) used for SYS-DMAC
DMA transfers are:

    Channel      R-Car H3    R-Car M3-W    R-Car M3-N
    -------------------------------------------------
    SYS-DMAC0    S0D3        S0D3          S0D3
    SYS-DMAC1    S3D1        S3D1          S3D1
    SYS-DMAC2    S3D1        S3D1          S3D1

As a result, change the parent clocks of the SYS-DMAC{1,2} module clocks
on R-Car H3, R-Car M3-W, and R-Car M3-N to S3D1.

NOTE: This information will be reflected in a future revision of the
      R-Car Gen3 Hardware Manual.

Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com>
[geert: Update RZ/G2M]
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Simon Horman <horms+renesas@verge.net.au>

...

This commit is contained in:

Takeshi Kihara 2018-09-28 16:18:00 +09:00 • committed by Geert Uytterhoeven

parent c2182095c8

commit 3c772f71a5

4 changed files with 8 additions and 8 deletions

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drivers/clk/renesas/r8a774a1-cpg-mssr.c

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drivers/clk/renesas/r8a7795-cpg-mssr.c

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drivers/clk/renesas/r8a7796-cpg-mssr.c

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drivers/clk/renesas/r8a77965-cpg-mssr.c

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