drm/i915: Only apply one barrier after a breadcrumb interrupt is posted

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If we flag the seqno as potentially stale upon receiving an interrupt,
we can use that information to reduce the frequency that we apply the
heavyweight coherent seqno read (i.e. if we wake up a chain of waiters).

v2: Use cmpxchg to replace READ_ONCE/WRITE_ONCE for more explicit
control of the ordering wrt to interrupt generation and interrupt
checking in the bottom-half.

Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Reviewed-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/1467390209-3576-14-git-send-email-chris@chris-wilson.co.uk

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This commit is contained in:

Chris Wilson 2016-07-01 17:23:23 +01:00

parent 7ec2c73b1d

commit 3d5564e910

4 changed files with 26 additions and 7 deletions

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15

drivers/gpu/drm/i915/i915_drv.h

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1

drivers/gpu/drm/i915/i915_irq.c

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16

drivers/gpu/drm/i915/intel_breadcrumbs.c

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1

drivers/gpu/drm/i915/intel_ringbuffer.h

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