clk: ingenic/jz4770: Fix incorrect dividers for main clocks

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The main clocks (cclk, h0clk, h1clk, h2clk, c1clk, pclk) were using
incorrect dividers, and thus reported an incorrect rate.

Signed-off-by: Paul Cercueil <paul@crapouillou.net>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>

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Paul Cercueil 2019-05-02 23:25:00 +02:00 • committed by Stephen Boyd

parent 2a1a703635

commit 44b06a76ad

1 changed files with 28 additions and 6 deletions

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drivers/clk/ingenic/jz4770-cgu.c

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