clk: meson: gxbb: let sar_adc_clk_div set the parent clock rate

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The meson-saradc driver manually sets the input clock for
sar_adc_clk_sel. Update the GXBB clock driver (which is used on GXBB,
GXL and GXM) so the rate settings on sar_adc_clk_div are propagated up
to sar_adc_clk_sel which will let the common clock framework select the
best matching parent clock if we want that.

This makes sar_adc_clk_div consistent with the axg-aoclk and g12a-aoclk
drivers, which both also specify CLK_SET_RATE_PARENT.

Fixes: 33d0fcdfe0 ("clk: gxbb: add the SAR ADC clocks and expose them")
Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>

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Martin Blumenstingl 2019-09-21 17:04:11 +02:00 • committed by Jerome Brunet

parent 54ecb8f702

commit 44b09b11b8

1 changed files with 1 additions and 0 deletions

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drivers/clk/meson/gxbb.c

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