ARM: tegra: Fix Beaver's PCIe lane configuration

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Beaver's PCIe lane configuration most closely matches x2 x2 x2 rather
than x4 x1 x1, since clocks 0 and 2 are used, and lanes 0 and 5 are used,
and the only way those align is with a x2 x2 x2 configuration.

Also, disable root port 1; there's nothing connected to it. Root port 0
is the on-board PCIe Ethernet, and port 2 is the mini-PCIe slot.

Signed-off-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Signed-off-by: Stephen Warren <swarren@nvidia.com>

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Stephen Warren 2013-08-09 16:49:29 +02:00

parent bb034cb5eb

commit 44fefab459

1 changed files with 4 additions and 4 deletions

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arch/arm/boot/dts/tegra30-beaver.dts

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