drm/msm/a6xx: Switch to GMU AO counter

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[ Upstream commit f195421318 ]

CP_ALWAYS_ON counter falls under GX domain which is collapsed during
IFPC. So switch to GMU_ALWAYS_ON counter for any CPU reads since it is
not impacted by IFPC. Both counters are clocked by same xo clock source.

Signed-off-by: Akhil P Oommen <akhilpo@oss.qualcomm.com>
Patchwork: https://patchwork.freedesktop.org/patch/673373/
Signed-off-by: Rob Clark <robin.clark@oss.qualcomm.com>
Signed-off-by: Sasha Levin <sashal@kernel.org>

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Akhil P Oommen 2025-09-08 13:57:02 +05:30 • committed by Greg Kroah-Hartman

parent ea44af1bd8

commit 469b6b0813

1 changed files with 16 additions and 14 deletions

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drivers/gpu/drm/msm/adreno/a6xx_gpu.c

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