clk: renesas: rzg2l: Add DSI divider clk support

Browse source

M3 clock is sourced from DSI Divider (DSIDIVA * DSIDIVB)

This patch add support for DSI divider clk by combining
DSIDIVA and DSIDIVB.

Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Link: https://lore.kernel.org/r/20220430114156.6260-4-biju.das.jz@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>

...

This commit is contained in:

Biju Das 2022-04-30 12:41:50 +01:00 • committed by Geert Uytterhoeven

parent 6cc859cae9

commit 46bb3e15e8

2 changed files with 136 additions and 0 deletions

Show all changes Ignore whitespace when comparing lines Ignore changes in amount of whitespace Ignore changes in whitespace at EOL

Download patch file Download diff file Expand all files Collapse all files

125

drivers/clk/renesas/rzg2l-cpg.c

View file

11

drivers/clk/renesas/rzg2l-cpg.h

View file