drm/i915/skl: Make gen8_irq_power_well_post_enable() take a pipe mask

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While we only need to restore pipe B/C interrupt registers on BDW when
enabling the power well, skylake a bit more flexible and we'll also need
to restore the pipe A registers as it has its own power well that can be
toggled.

Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>

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Damien Lespiau 2015-03-06 18:50:48 +00:00 • committed by Daniel Vetter

parent 5575f03a60

commit 4c6c03be12

3 changed files with 14 additions and 7 deletions

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15

drivers/gpu/drm/i915/i915_irq.c

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3

drivers/gpu/drm/i915/intel_drv.h

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3

drivers/gpu/drm/i915/intel_runtime_pm.c

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