drm/i915/cx0: Drop C20 25.175 MHz rate

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Drop C20 25.175 MHz PLL table as with these
PLL dividers the port clock will be incorrectly
calculated to 25.2 MHz. For 25.175 MHz rate the
PLl dividers are calculated algorithmically making
PLL table for this rate redundant.

Signed-off-by: Mika Kahola <mika.kahola@intel.com>
Reviewed-by: Suraj Kandpal <suraj.kandpal@intel.com>
Link: https://patch.msgid.link/20260119093757.2850233-14-mika.kahola@intel.com

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Mika Kahola 2026-01-19 09:37:54 +00:00

parent 10d187b356

commit 4fa244583e

1 changed files with 0 additions and 26 deletions

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drivers/gpu/drm/i915/display/intel_cx0_phy.c

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